Dillon Varone 689932a8dd drm/amd/display: Implement FIFO enable sequence on DCN32 ... [WHY?] FIFO enable sequence is incomplete as it is currently implemented in FW, and requires reset to prevent the FIFO to be enabled in an invalid state. This cannot be done until DIG FE is connected to the BE. [HOW?] Add FIFO enable sequence in driver for dcn32 with reset after DIG FE is connected to BE. Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-01-13 14:57:23 -05:00
..
amdgpu_dm	drm/amd/display: Conversion to bool not necessary	2023-01-13 14:54:51 -05:00
dc	drm/amd/display: Implement FIFO enable sequence on DCN32	2023-01-13 14:57:23 -05:00
dmub	drm/amd/display: Update BW alloc after new DMUB logic	2023-01-13 14:56:15 -05:00
include	drm/amd/display: add support for three new square pattern variants from DP2.1 specs	2022-12-15 12:18:19 -05:00
modules	drm/amd/display: fix PSR-SU/DSC interoperability support	2023-01-09 17:02:18 -05:00
Kconfig	drm/amd/display: add DCN support for ARM64	2022-11-04 16:05:54 -04:00
Makefile
TODO