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We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326 platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the usb480m clk to critical because GPU 480M is from usb480m and the source clocks should be always on. And the usb phy 480MHz clk is parent of usb480m clk, so the clk framework will prepare the usb phy 480MHz clk when register it. This logic works well if the usb phy probe only once. But if the usb phy needs to probe twice or more because of some reasons (e.g. fail to get vbus regulator from RK819), the usb phy 480MHz clk will be unregistered and registered again, however, the clk framework doesn't prepare the usb phy 480MHz clk except the first time register operation. So we move the 480MHz clk register to the end of probe, and make sure only register it once. Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5 Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Bin Yang <yangbin@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> |
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| allwinner | ||
| amlogic | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| motorola | ||
| mscc | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| st | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||