Michael Tretter 846307185f drm/bridge: samsung-dsim: update PLL reference clock ... The PLL requires a clock frequency in a certain platform-dependent range after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to the upper limit before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de		2023-10-09 11:06:22 +02:00
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analogix_dp.h	drm/bridge: analogix_dp: Split bind() into probe() and real bind()	2020-04-09 10:29:35 +02:00
dw_hdmi.h	drm/bridge: dw-hdmi: change YUV420 selection logic at clock setup	2023-06-27 09:51:31 +02:00
dw_mipi_dsi.h	drm/bridge/synopsys: dsi: extend the prototype of mode_valid()	2022-01-04 12:53:59 +01:00
mhl.h	drm/bridge/mhl.h: Replace zero-length array with flexible-array member	2020-03-06 11:52:01 +01:00
samsung-dsim.h	drm/bridge: samsung-dsim: update PLL reference clock	2023-10-09 11:06:22 +02:00