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The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
parameter's unit is Unit Interval(UI) and the minimum value is 8. Also,
kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy
mentions that it should be in UI. However, the dphy core driver wrongly
sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds.
So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE
parameter's minimum value according to the D-PHY specification.
I'm assuming that all impacted custom drivers shall program values in
TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY
specification mentions that the frequency of TxByteClkHS is exactly 1/8
the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant
custom driver code is changed to program those values as
DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then.
Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK.
Help is needed to test with other i.MX8mq, Meson and Rockchip platforms,
as I don't have the hardwares.
Fixes:
|
||
|---|---|---|
| .. | ||
| adv7511 | ||
| analogix | ||
| cadence | ||
| synopsys | ||
| cdns-dsi.c | ||
| chipone-icn6211.c | ||
| chrontel-ch7033.c | ||
| cros-ec-anx7688.c | ||
| display-connector.c | ||
| ite-it66121.c | ||
| Kconfig | ||
| lontium-lt8912b.c | ||
| lontium-lt9611.c | ||
| lontium-lt9611uxc.c | ||
| lvds-codec.c | ||
| Makefile | ||
| megachips-stdpxxxx-ge-b850v3-fw.c | ||
| nwl-dsi.c | ||
| nwl-dsi.h | ||
| nxp-ptn3460.c | ||
| panel.c | ||
| parade-ps8622.c | ||
| parade-ps8640.c | ||
| sii902x.c | ||
| sii9234.c | ||
| sil-sii8620.c | ||
| sil-sii8620.h | ||
| simple-bridge.c | ||
| tc358762.c | ||
| tc358764.c | ||
| tc358767.c | ||
| tc358768.c | ||
| tc358775.c | ||
| thc63lvd1024.c | ||
| ti-sn65dsi83.c | ||
| ti-sn65dsi86.c | ||
| ti-tfp410.c | ||
| ti-tpd12s015.c | ||