Krzysztof Kozlowski 5a97bc924a drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver ... PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux clock from Common Clock Framework: devm_clk_hw_register_mux_parent_hws(). There could be a path leading to concurrent and conflicting updates between PHY driver and clock framework, e.g. changing the mux and enabling PLL clocks. Add dedicated spinlock to be sure all PHY_CMN_CLK_CFG1 updates are synchronized. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d14 ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/637378/ Link: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-2-0943b850722c@linaro.org Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>		2025-02-15 11:46:42 -08:00
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drm	drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver	2025-02-15 11:46:42 -08:00
host1x	gpu: host1x: Set up device DMA parameters	2024-10-15 18:46:25 +02:00
ipu-v3	Driver core changes for 6.11-rc1	2024-07-25 10:42:22 -07:00
trace
vga	drm: Do delayed switcheroo in drm_lastclose()	2024-08-13 16:21:07 +02:00
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