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The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM interface the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM interface has written the message to SRAM. Add support for the Samsung Exynos mailbox controller. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> |
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| .. | ||
| arm_mhuv2_message.h | ||
| brcm-message.h | ||
| exynos-message.h | ||
| mchp-ipc.h | ||
| mtk-cmdq-mailbox.h | ||
| zynqmp-ipi-message.h | ||