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BAM version 1.6.0 and later changed the behavior of the mask field in
command elements for read operations.
In older BAM versions, or prior implementation assumptions, the mask
field was effectively ignored for read commands. However, starting from
BAM v1.6.0, the mask field for read commands is repurposed to carry the
upper 4 bits of the destination address, enabling support for 36-bit
addressing. For write commands, the mask field continues to function as
a traditional write mask.
The current driver sets mask = 0xffffffff for all command elements.
While this works for write operations, it breaks read operations on
BAM v1.6.0+ hardware. In such cases, the hardware interprets the upper
address bits as 0xf, resulting in an invalid destination address
(0xf_xxxxxxxx instead of 0x0_xxxxxxxx).
This leads to failures such as NAND enumeration issues observed on
platforms like IPQ5424.
Fix this by assigning the mask field based on command type:
- For read commands: set mask = 0 (upper address bits = 0)
- For write commands: retain mask = 0xffffffff
Also update the bam_cmd_element structure documentation to reflect the
dual purpose of the mask field across BAM versions.
This ensures correct behavior on BAM v1.6.0+ while maintaining backward
compatibility with older hardware.
Fixes:
|
||
|---|---|---|
| .. | ||
| amd_xdma.h | ||
| dw.h | ||
| edma.h | ||
| hsu.h | ||
| idma64.h | ||
| imx-dma.h | ||
| k3-event-router.h | ||
| k3-psil.h | ||
| k3-udma-glue.h | ||
| mxs-dma.h | ||
| pxa-dma.h | ||
| qcom_adm.h | ||
| qcom_bam_dma.h | ||
| qcom-gpi-dma.h | ||
| sprd-dma.h | ||
| ti-cppi5.h | ||
| xilinx_dma.h | ||
| xilinx_dpdma.h | ||