linux/include/uapi/drm
Pranjal Ramajor Asha Kanojiya 3b511278b6 accel/qaic: Support for 0 resize slice execution in BO
Add support to partially execute a slice which is resized to zero.
Executing a zero size slice in a BO should mean that there is no DMA
transfers involved but you should still configure doorbell and semaphores.

For example consider a BO of size 18K and it is sliced into 3 6K slices
and user calls partial execute ioctl with resize as 10K.
slice 0 - size is 6k and offset is 0, so resize of 10K will not cut short
          this slice hence we send the entire slice for execution.
slice 1 - size is 6k and offset is 6k, so resize of 10K will cut short this
          slice and only the first 4k should be DMA along with configuring
          doorbell and semaphores.
slice 2 - size is 6k and offset is 12k, so resize of 10k will cut short
          this slice and no DMA transfer would be involved but we should
          would configure doorbell and semaphores.

This change begs to change the behavior of 0 resize. Currently, 0 resize
partial execute ioctl behaves exactly like execute ioctl i.e. no resize.
After this patch all the slice in BO should behave exactly like slice 2 in
above example.

Refactor copy_partial_exec_reqs() to make it more readable and less
complex.

Signed-off-by: Pranjal Ramajor Asha Kanojiya <quic_pkanojiy@quicinc.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231027164330.11978-1-quic_jhugo@quicinc.com
2023-11-03 09:03:01 -06:00
..
amdgpu_drm.h drm/amdgpu: add UAPI for allocating doorbell memory 2023-08-07 17:14:06 -04:00
armada_drm.h License cleanup: add SPDX license identifier to uapi header files with a license 2017-11-02 11:20:11 +01:00
drm_fourcc.h drm/fourcc: Add NV20 and NV30 YUV formats 2023-10-24 21:34:35 +02:00
drm_mode.h drm: introduce CLOSEFB IOCTL 2023-10-27 13:47:56 +02:00
drm_sarea.h drm: add extern C guard for the UAPI headers 2016-05-13 13:57:17 +01:00
drm.h drm: introduce CLOSEFB IOCTL 2023-10-27 13:47:56 +02:00
etnaviv_drm.h drm/etnaviv: provide more ID values via GET_PARAM ioctl. 2021-01-22 12:33:57 +01:00
exynos_drm.h drm/exynos: Rename Exynos to lowercase 2020-01-21 09:09:42 +09:00
habanalabs_accel.h accel/habanalabs: add description to several info ioctls 2023-06-08 12:35:56 +03:00
i915_drm.h drm/i915: Allow user to set cache at BO creation 2023-06-07 17:32:15 +02:00
ivpu_accel.h accel/ivpu: Document DRM_IVPU_PARAM_CAPABILITIES 2023-08-11 10:48:23 +02:00
lima_drm.h drm/lima: support heap buffer creation 2020-01-27 22:01:09 +08:00
msm_drm.h drm/msm: Rename drm_msm_gem_submit_reloc::or in C++ code 2023-04-06 20:29:39 +03:00
nouveau_drm.h drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitly 2023-08-24 02:57:50 +02:00
omap_drm.h Revert "drm/omap: add OMAP_BO flags to affect buffer allocation" 2019-10-23 10:41:41 -04:00
panfrost_drm.h drm/panfrost: Remove type name from internal struct again 2022-11-07 15:35:43 +00:00
qaic_accel.h accel/qaic: Support for 0 resize slice execution in BO 2023-11-03 09:03:01 -06:00
qxl_drm.h drm/qxl: fix __user annotations 2017-06-23 10:06:31 +02:00
radeon_drm.h drm/radeon: add extern C guard for the UAPI header 2016-05-13 14:06:14 +01:00
tegra_drm.h drm/tegra: Add new UAPI to header 2021-08-10 14:48:17 +02:00
v3d_drm.h drm/v3d: update UAPI to match user-space for V3D 7.x 2023-11-02 08:54:39 -03:00
vc4_drm.h drm/vc4: Add a pad field to align drm_vc4_submit_cl to 64 bits. 2018-05-03 15:20:09 -07:00
vgem_drm.h drm/vgem: Attach sw fences to exported vGEM dma-buf (ioctl) 2016-07-18 08:54:55 +02:00
virtgpu_drm.h drm/virtio: Support sync objects 2023-08-01 01:41:04 +03:00
vmwgfx_drm.h drm/vmwgfx: Allow querying of the SVGA PCI id from the userspace 2022-03-11 13:29:35 -05:00