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42eeed6d9f
Add support for RZ/G3E RSCI. RSCI IP found on the RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. It has 6 clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module clocks + 1 external clock) on T2H, has 6 irqs compared to 4 on RZ/T2H and has multiple resets. Add support for the hardware flow control. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20251129164325.209213-18-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
12 lines
224 B
C
12 lines
224 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RSCI_H__
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#define __RSCI_H__
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#include "sh-sci-common.h"
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extern struct sci_of_data of_rsci_rzg3e_data;
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extern struct sci_of_data of_rsci_rzt2h_data;
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#endif /* __RSCI_H__ */
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