linux/arch/riscv
Atish Patra 3ab75a793e RISC-V: KVM: Remove 's' & 'u' as valid ISA extension
There are no ISA extension defined as 's' & 'u' in RISC-V specifications.
The misa register defines 's' & 'u' bit as Supervisor/User privilege mode
enabled. But it should not appear in the ISA extension in the device tree.

Remove those from the allowed ISA extension for kvm.

Fixes: a33c72faf2 ("RISC-V: KVM: Implement VCPU create, init and
destroy functions")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
2022-04-20 13:42:49 +05:30
..
boot RISC-V Patches for the 5.18 Merge Window, Part 2 2022-04-01 13:31:57 -07:00
configs RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n 2022-03-31 17:19:27 -07:00
errata riscv: errata: alternative: mark vendor_patch_func __initdata 2022-01-09 11:02:46 -08:00
include RISC-V Patches for the 5.18 Merge Window, Part 2 2022-04-01 13:31:57 -07:00
kernel RISC-V Patches for the 5.18 Merge Window, Part 2 2022-04-01 13:31:57 -07:00
kvm RISC-V: KVM: Remove 's' & 'u' as valid ISA extension 2022-04-20 13:42:49 +05:30
lib riscv: Fixed misaligned memory access. Fixed pointer comparison. 2022-03-10 10:24:04 -08:00
mm RISC-V Patches for the 5.18 Merge Window, Part 1 2022-03-25 10:11:38 -07:00
net riscv: bpf: Fix eBPF's exception tables 2022-01-19 10:50:02 -08:00
Kbuild kbuild: use more subdir- for visiting subdirectories while cleaning 2021-10-24 13:49:46 +09:00
Kconfig RISC-V CPU Idle Support 2022-03-30 16:17:54 -07:00
Kconfig.debug
Kconfig.erratas riscv: alternative only works on !XIP_KERNEL 2022-03-10 10:05:19 -08:00
Kconfig.socs RISC-V CPU Idle Support 2022-03-30 16:17:54 -07:00
Makefile riscv: fix build with binutils 2.38 2022-02-10 09:17:01 -08:00