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Some of DesignWare core's DBI registers (a.k.a configuration space registers) are write-protected with a lock without enabling which they are read-only by default. These write-protected registers are implementation specific. Tegra194's BAR-0 register which is at offset 0x10 in the configuration space is an example. Current implementation in dw_pcie_setup_rc() API attempts to unlock those write-protected registers whenever they are updated and lock them back again for writing. Group all write-protected registers writes so that locking and unlocking is performed once to avoid bloating the code with multiple unlock/lock sequences for all those write-protected registers. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> |
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| .. | ||
| dwc | ||
| Kconfig | ||
| Makefile | ||
| pci-aardvark.c | ||
| pci-ftpci100.c | ||
| pci-host-common.c | ||
| pci-host-generic.c | ||
| pci-hyperv.c | ||
| pci-mvebu.c | ||
| pci-rcar-gen2.c | ||
| pci-tegra.c | ||
| pci-thunder-ecam.c | ||
| pci-thunder-pem.c | ||
| pci-v3-semi.c | ||
| pci-versatile.c | ||
| pci-xgene-msi.c | ||
| pci-xgene.c | ||
| pcie-altera-msi.c | ||
| pcie-altera.c | ||
| pcie-cadence-ep.c | ||
| pcie-cadence-host.c | ||
| pcie-cadence.c | ||
| pcie-cadence.h | ||
| pcie-iproc-bcma.c | ||
| pcie-iproc-msi.c | ||
| pcie-iproc-platform.c | ||
| pcie-iproc.c | ||
| pcie-iproc.h | ||
| pcie-mediatek.c | ||
| pcie-mobiveil.c | ||
| pcie-rcar.c | ||
| pcie-rockchip-ep.c | ||
| pcie-rockchip-host.c | ||
| pcie-rockchip.c | ||
| pcie-rockchip.h | ||
| pcie-tango.c | ||
| pcie-xilinx-nwl.c | ||
| pcie-xilinx.c | ||
| vmd.c | ||