Alex Sierra 36a1707afd drm/amdgpu: modify packet size for pm4 flush tlbs ... [Why] PM4 packet size for flush message was oversized. [How] Packet size adjusted to allocate flush + fence packets. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-01-22 16:33:52 -05:00
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drm	drm/amdgpu: modify packet size for pm4 flush tlbs	2020-01-22 16:33:52 -05:00
host1x	drm/tegra: Changes for v5.6-rc1	2020-01-15 16:21:28 +10:00
ipu-v3
vga	vga: Fix Kconfig indentation	2019-11-20 17:40:32 +01:00
Makefile