Zhang Yubing 530d2fa793 drm/rockchip: vop2: get hdmi phy clk rate rate before set ... hdmi phy clk rate may change by hdmi controller, while clk framework don't know that, whick may set wrong dclk rate when use hdmi phy pll as dclk parent. So It necessary to update the hdmi phy pll clk rate before set a new clk rate. Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com> Change-Id: I4ca6d5e34f0459ecbcfa894e9a136d05408160a0		2022-04-12 15:24:21 +08:00
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arm	MALI: bifrost: Change clock source to normal pll when suspend	2022-04-01 09:33:18 +08:00
drm	drm/rockchip: vop2: get hdmi phy clk rate rate before set	2022-04-12 15:24:21 +08:00
host1x	gpu: host1x: Split up client initalization and registration	2021-06-18 10:00:04 +02:00
ipu-v3	gpu: ipu-v3: Fix i.MX IPU-v3 offset calculations for (semi)planar U/V formats	2021-09-08 08:49:00 +02:00
trace	rk: revert to v4.19	2021-03-17 18:05:39 +08:00
vga	rk: revert to v4.19	2021-03-17 18:05:39 +08:00
Makefile	GPU: Kconfig: add gpu Kconfig to video Kconfig	2021-07-09 09:26:18 +08:00