mirror of
https://github.com/torvalds/linux.git
synced 2026-09-14 16:10:02 +02:00
core: - add docbook for DRM_IOCTL_SYNCOBJ_EVENTFD - change signature of drm_connector_attach_hdr_output_metadata_property - dedup counter and timestamp retrieval in vblank code - parse AMD VSDB v3 in CTA extension blocks - add P230, Y7, XYYY2101010, T430, XVUY210101010 formats - don't call drop master on file close if not master - use drm_printf_indent in atomic / bridge - fix 32b format descriptions - docs: fix toctree - hdmi: add common TMDS character rates - fix drm_syncobj_find_fence leak rust: - introduce Higher-Ranked lifetime types - replace drvdata with scoped registration data - add GPUVM immediate mode abstraction for rust GPU drivers - introduce DeviceContext type state for drm::Device bridge: - clarify drm_bridge_get/put - create drm_get_bridge_by_endpoint and use it - analogix_dp: add panel probing - ite-it6211 - use drm audio hdmi helpers buddy: - add lockdep annotations dp: - add PR and VRR updates - mst: fix buffer overflows - add Adaptive Sync SDP decoding support - fix OOB reads in dp-mst ttm: - bump fpfn/lpfn to 64-bit scheduler: - change default to fair scheduler - map runqueue 1:1 with scheduler dma-buf: - port selftests to kunit - convert dma-buf system/heap allocators to module - add separate DMABUF_HEAPS_SYSTEM_CC_SHARED Kconfig udmabuf: - revert hugetlb support - fix error with CONFIG_DMA_API_DEBUG dma-fence: - fix tracepoints lifetime - remove unused signal on any support ras: - add clear error counter netlink command to drm ras gpusvm: - reject VMAs with VM_IO or VM_PFNMAP when creating SVM ranges - use IOVA allocations pagemap: - use IOVA allocations panels: - update to use ref counts - add support for CSW PNB601LS1-2, LGD LP116WHA-SPB1 - add support for waveshare panels - CMN N116BCN-EA1, CMN N140HCA-EEK, IVO M140NWFQ R5, - IVO, R140NWFW R0, BOE NT140*, BOE NV133FHM-N4F, - AUO B140*, AUO B133HAN06.6 and AUO B116XTN02.3 eDP panels - Surface Pro 12 Panel xe: - add CRI PCI-IDs - debugfs add multi-lrc info - engine init cleanup - PF fair scheduling auto provisioning - system controller support for CRI/Xe3p - PXP state machine fixes - Reset/wedge/unload corner case fixes - Wedge path memory allocation fixes - PAT type cleanups - Reject unsafe PAT for CPU cached memory - OA improvements for CRI device memory - kernel doc syntax in xe headers - xe_drm.h documentation fixes - include guard cleanups - VF CCS memory pool - i915/xe step unification - Xe3p GT tuning fixes - forcewake cleanup in GT and GuC - admin-only PF mode - enable hwmon energy attributes for CRI - enable GT_MI_USER_INTERRUPT - refactor emit functions - oa workarounds - multi_queue: allow QUEUE_TIMESTAMP register - convert stolen memory to ttm range manager - use xe2 style blitter as a feature flag - make drm_driver const - add/use IRQ page to HW engine definition - fix oops when display disabled i915: - enable PIPEDMC_ERROR interrupt - more common display code refactoring - restructure DP/HDMI sink format handling - eliminate FB usage from lowlevel pinning code - panel replay bw optimization - integrate sharpness filter into the scaler - new fb_pin abstraction for xe/i915 fb transparent handling - skip inactive MST connectors on HDCP - start switching to display specific registers - use polling when irq unavailable - Adaptive-sync SDP prep amdgpu: - use drm_display_info for AMD VSDB data - Initial HDMI 2.1 FRL support - Initial DCN 4.2.1 support - GART fixes for non-4k pages - GC 11.5.6/SDMA 6.4.0/and other new IPs - GFX9/DCE6/Hawaii/SDMA4/GART/Userq fixes - Finish support for using multiple SDMA queues for TTM operations - SWSMU updates - GC 12.1 updates - SMU 15.0.8 updates - DCN 4.2 updates - DC type conversion fixes - Enable DC power module - Replay/PSR updates - SMU 13.x updates - Compute queue quantum MQD updates - ASPM fix - Align VKMS with common implementation - DC analog support fixes - UVD 3 fixes - TCC harvesting fixes for SI - GC 11 APU module reload fix - NBIO 6.3.2 support - IH 7.1 updates - DC cursor fixes - VCN/JPEG user fence fixes - DC support for connectors without DDC - Prefer ROM BAR for default VGA device - DC bandwidth fixes - Add PTL support for profiler - Introduce dc_plane_cm and migrate surface update color path - Add FRL registers for HDMI 2.1 - Restructure VM state machine - Auxless ALPM support - GEM_OP locking/warning fixes - switch to system_dfl_wq amdkfd: - GPUVM TLB flush fix - Hotplug fix - Boundary check fixes - SVM fixes - CRIU fixes - add profiler API - MES 12.1 updates msm: - core: - fix shrinker documentation - IFPC enabled for gen8 - PERFCNTR_CONFIG ioctl support - GPU: - reworked UBWC handling - a810 support - MDSS: - add support for Milos platform - reworked UBWC handling - DisplayPort: - reworked HPD handling as prep for MST - DPU: - Milos platform support - reworked UBWC handling - DSI: - Milos platform support nova: - Hopper/Blackwell enablement (GH100/GB100/GB202) - FSP support - 32-bit firmware support - HAL functions - refactor GSP boot/unload - GA100 support - VBIOS hardening/refactoring - Adopt higher order lifetime types tyr: - define register blocks - add shmem backed GEM objects - adopt higher order lifetime types - move clock cleanup into Drop radeon: - Hawaii SMU fixes - CS parser fix - use struct drm_edid instead of edid amdxdna: - export per-client BO memory via fdinfo - AIE4 device support - support medium/lower power modes - expandable device heap support - revert read-only user-pointer BO mappings ivpu: - support frequency limiting panthor: - enable GEM shrinker support - add eviction and reclaim info to fdinfo v3d: - enable runtime PM mgag200: - support XRGB1555 + C8 ast: - support XRGB1555 + C8 - use constants for lots of registers - fix register handling imagination: - fence handling refactoring nouveau: - fix sched double call - expose VBIOS on GSP-RM systems - add GA100 support virtio: - add VIRTIO_GPU_F_BLOB_ALIGNMENT flag - add deferred mapping support gud: - add RCade Display Adapter hibmc: - fix no connectors usage mediatek: - hdmi: convert error handling - simplify mtk_crtc allocation exynos: - move fbdev emulation to drm client buffers - use drm format helpers for geometry/size - adopt core DMA tracking - fix framebuffer offset handling renesas: - add RZ/T2H SOC support versilicon: - add cursor plane support tegra: - use drm client for framebuffer -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmoyOXkACgkQDHTzWXnE hr5Pxg//VwqDYgf8CwWtLwXqHYBhGDwj1PDA/zLoosm32fXABKhzPMA5XcaPHBKh Y7Wyo7988cxXFQ0BRltKP1S3d04ck5ZbBA/qpwwX9Pz0u8HhNMicwLd9ASlWqqkP ogFIj3J8PsjlTMVI2cnzQ7s0TMQoQorUaNl13vQnITDPSNncCAunrKixpzVagHeK /ARlIg4kqSbvlKAhkvps7FbJUG3l/g901HdAcspp0bn6d3+4zz8Yg+yg/b4Xngdh Sn6UGDxwrNeBSHP2Spj5/rGSOuo4L8Fr1rS0+KEwRnEqrg+qdq9mo9l0xQsJV9/e 4ql6nssEMC/CIHwHomsgCdxdOsj2DiXLUucJKBwavHHSWNHFgdLhNSdaUcwrkui3 sLmahOEXFwFIR3K1X++547Wux9DhAWDcvq/SnxzN0dQBpN0AmpE0/o/3Vb7Vw4dO /cfvI4Y1WGviJCs58p36tqYGx8dDPuMh9tiUtQvBXBkkS87MqBX8wM49qHSlzEOV EkQfGV1cLMBJpZZkMezrqCNyIS7ghzXJ+K/IruAPrgvN7/kCY7hRclUT+Z/1Mqvc mw3Japbcy7P+BMKnlNfCZsDXg04kYZC5MOaMeiJOLg6qfHBHITD8gP1zct+RikIS d+43kYwt43dPj53jUUXpREoAezSoF2ktncFChB2tdeaMlb6oJIM= =86oS -----END PGP SIGNATURE----- Merge tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel Pull drm updates from Dave Airlie: "Highlights: - xe: add initial CRI platform support - amdgpu: initial HDMI 2.1 FRL support - rust: add some new type concepts for device lifetimes - scheduler: moves to a fair algorithm and lots of cleanups But it's mostly the usual mountain of changes across the board. core: - add docbook for DRM_IOCTL_SYNCOBJ_EVENTFD - change signature of drm_connector_attach_hdr_output_metadata_property - dedup counter and timestamp retrieval in vblank code - parse AMD VSDB v3 in CTA extension blocks - add P230, Y7, XYYY2101010, T430, XVUY210101010 formats - don't call drop master on file close if not master - use drm_printf_indent in atomic / bridge - fix 32b format descriptions - docs: fix toctree - hdmi: add common TMDS character rates - fix drm_syncobj_find_fence leak rust: - introduce Higher-Ranked lifetime types - replace drvdata with scoped registration data - add GPUVM immediate mode abstraction for rust GPU drivers - introduce DeviceContext type state for drm::Device bridge: - clarify drm_bridge_get/put - create drm_get_bridge_by_endpoint and use it - analogix_dp: add panel probing - ite-it6211 - use drm audio hdmi helpers buddy: - add lockdep annotations dp: - add PR and VRR updates - mst: fix buffer overflows - add Adaptive Sync SDP decoding support - fix OOB reads in dp-mst ttm: - bump fpfn/lpfn to 64-bit scheduler: - change default to fair scheduler - map runqueue 1:1 with scheduler dma-buf: - port selftests to kunit - convert dma-buf system/heap allocators to module - add separate DMABUF_HEAPS_SYSTEM_CC_SHARED Kconfig udmabuf: - revert hugetlb support - fix error with CONFIG_DMA_API_DEBUG dma-fence: - fix tracepoints lifetime - remove unused signal on any support ras: - add clear error counter netlink command to drm ras gpusvm: - reject VMAs with VM_IO or VM_PFNMAP when creating SVM ranges - use IOVA allocations pagemap: - use IOVA allocations panels: - update to use ref counts - add support for CSW PNB601LS1-2, LGD LP116WHA-SPB1 - add support for waveshare panels - CMN N116BCN-EA1, CMN N140HCA-EEK, IVO M140NWFQ R5, - IVO, R140NWFW R0, BOE NT140*, BOE NV133FHM-N4F, - AUO B140*, AUO B133HAN06.6 and AUO B116XTN02.3 eDP panels - Surface Pro 12 Panel xe: - add CRI PCI-IDs - debugfs add multi-lrc info - engine init cleanup - PF fair scheduling auto provisioning - system controller support for CRI/Xe3p - PXP state machine fixes - Reset/wedge/unload corner case fixes - Wedge path memory allocation fixes - PAT type cleanups - Reject unsafe PAT for CPU cached memory - OA improvements for CRI device memory - kernel doc syntax in xe headers - xe_drm.h documentation fixes - include guard cleanups - VF CCS memory pool - i915/xe step unification - Xe3p GT tuning fixes - forcewake cleanup in GT and GuC - admin-only PF mode - enable hwmon energy attributes for CRI - enable GT_MI_USER_INTERRUPT - refactor emit functions - oa workarounds - multi_queue: allow QUEUE_TIMESTAMP register - convert stolen memory to ttm range manager - use xe2 style blitter as a feature flag - make drm_driver const - add/use IRQ page to HW engine definition - fix oops when display disabled i915: - enable PIPEDMC_ERROR interrupt - more common display code refactoring - restructure DP/HDMI sink format handling - eliminate FB usage from lowlevel pinning code - panel replay bw optimization - integrate sharpness filter into the scaler - new fb_pin abstraction for xe/i915 fb transparent handling - skip inactive MST connectors on HDCP - start switching to display specific registers - use polling when irq unavailable - Adaptive-sync SDP prep amdgpu: - use drm_display_info for AMD VSDB data - Initial HDMI 2.1 FRL support - Initial DCN 4.2.1 support - GART fixes for non-4k pages - GC 11.5.6/SDMA 6.4.0/and other new IPs - GFX9/DCE6/Hawaii/SDMA4/GART/Userq fixes - Finish support for using multiple SDMA queues for TTM operations - SWSMU updates - GC 12.1 updates - SMU 15.0.8 updates - DCN 4.2 updates - DC type conversion fixes - Enable DC power module - Replay/PSR updates - SMU 13.x updates - Compute queue quantum MQD updates - ASPM fix - Align VKMS with common implementation - DC analog support fixes - UVD 3 fixes - TCC harvesting fixes for SI - GC 11 APU module reload fix - NBIO 6.3.2 support - IH 7.1 updates - DC cursor fixes - VCN/JPEG user fence fixes - DC support for connectors without DDC - Prefer ROM BAR for default VGA device - DC bandwidth fixes - Add PTL support for profiler - Introduce dc_plane_cm and migrate surface update color path - Add FRL registers for HDMI 2.1 - Restructure VM state machine - Auxless ALPM support - GEM_OP locking/warning fixes - switch to system_dfl_wq amdkfd: - GPUVM TLB flush fix - Hotplug fix - Boundary check fixes - SVM fixes - CRIU fixes - add profiler API - MES 12.1 updates msm: - core: - fix shrinker documentation - IFPC enabled for gen8 - PERFCNTR_CONFIG ioctl support - GPU: - reworked UBWC handling - a810 support - MDSS: - add support for Milos platform - reworked UBWC handling - DisplayPort: - reworked HPD handling as prep for MST - DPU: - Milos platform support - reworked UBWC handling - DSI: - Milos platform support nova: - Hopper/Blackwell enablement (GH100/GB100/GB202) - FSP support - 32-bit firmware support - HAL functions - refactor GSP boot/unload - GA100 support - VBIOS hardening/refactoring - Adopt higher order lifetime types tyr: - define register blocks - add shmem backed GEM objects - adopt higher order lifetime types - move clock cleanup into Drop radeon: - Hawaii SMU fixes - CS parser fix - use struct drm_edid instead of edid amdxdna: - export per-client BO memory via fdinfo - AIE4 device support - support medium/lower power modes - expandable device heap support - revert read-only user-pointer BO mappings ivpu: - support frequency limiting panthor: - enable GEM shrinker support - add eviction and reclaim info to fdinfo v3d: - enable runtime PM mgag200: - support XRGB1555 + C8 ast: - support XRGB1555 + C8 - use constants for lots of registers - fix register handling imagination: - fence handling refactoring nouveau: - fix sched double call - expose VBIOS on GSP-RM systems - add GA100 support virtio: - add VIRTIO_GPU_F_BLOB_ALIGNMENT flag - add deferred mapping support gud: - add RCade Display Adapter hibmc: - fix no connectors usage mediatek: - hdmi: convert error handling - simplify mtk_crtc allocation exynos: - move fbdev emulation to drm client buffers - use drm format helpers for geometry/size - adopt core DMA tracking - fix framebuffer offset handling renesas: - add RZ/T2H SOC support versilicon: - add cursor plane support tegra: - use drm client for framebuffer" * tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel: (1731 commits) dma-buf: move system_cc_shared heap under separate Kconfig accel/amdxdna: Clear sva pointer after unbind agp/amd64: Fix broken error propagation in agp_amd64_probe() accel/amdxdna: Require carveout when PASID and force_iova are disabled drm/amdkfd: always resume_all after suspend_all drm/amdgpu/gfx: move fault and EOP IRQ get/put to hw_init/hw_fini drm/amd/display: Consult MCCS FreeSync cap only if requested & supported drm/amd/pm: Use strscpy in profile mode parsing drm/amdkfd: Fix infinite loop parsing CRAT with zero subtype length drm/amdkfd: fix sysfs topology prop length on buffer truncation drm/amdgpu: drop retry loop in amdgpu_hmm_range_get_pages drm/amd/pm: bound OD parameter parsing to stack array size drm/amd/pm: Stop pp_od_clk_voltage emit at PAGE_SIZE drm/amdkfd: Unwind debug trap enable on copy_to_user failure drm/amdgpu: validate the mes firmware version for gfx12.1 drm/amdgpu: validate the mes firmware version for gfx12 drm/amdgpu: compare MES firmware version ucode for gfx11 drm/amdkfd: Add bounds check for AMDKFD_IOC_WAIT_EVENTS drm/amdgpu: restart the CS if some parts of the VM are still invalidated drm/amd/display: use unsigned types for local pipe and REG_GET counters ...
666 lines
21 KiB
Rust
666 lines
21 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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//! Contains structures and functions dedicated to the parsing, building and patching of firmwares
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//! to be loaded into a given execution unit.
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use core::marker::PhantomData;
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use core::ops::Deref;
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use kernel::{
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device,
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firmware,
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prelude::*,
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str::CString,
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transmute::FromBytes, //
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};
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use crate::{
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falcon::{
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FalconDmaLoadTarget,
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FalconFirmware, //
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},
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gpu,
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num::{
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FromSafeCast,
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IntoSafeCast, //
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},
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};
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pub(crate) mod booter;
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pub(crate) mod fsp;
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pub(crate) mod fwsec;
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pub(crate) mod gsp;
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pub(crate) mod riscv;
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pub(crate) const FIRMWARE_VERSION: &str = "570.144";
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/// Requests the GPU firmware `name` suitable for `chipset`, with version `ver`.
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fn request_firmware(
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dev: &device::Device,
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chipset: gpu::Chipset,
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name: &str,
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ver: &str,
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) -> Result<firmware::Firmware> {
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let chip_name = chipset.name();
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CString::try_from_fmt(fmt!("nvidia/{chip_name}/gsp/{name}-{ver}.bin"))
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.and_then(|path| firmware::Firmware::request(&path, dev))
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}
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/// Structure used to describe some firmwares, notably FWSEC-FRTS.
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#[repr(C)]
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#[derive(Debug, Clone, FromBytes)]
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pub(crate) struct FalconUCodeDescV2 {
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/// Header defined by 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC*' in OpenRM.
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hdr: u32,
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/// Stored size of the ucode after the header, compressed or uncompressed
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stored_size: u32,
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/// Uncompressed size of the ucode. If store_size == uncompressed_size, then the ucode
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/// is not compressed.
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pub(crate) uncompressed_size: u32,
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/// Code entry point
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pub(crate) virtual_entry: u32,
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/// Offset after the code segment at which the Application Interface Table headers are located.
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pub(crate) interface_offset: u32,
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/// Base address at which to load the code segment into 'IMEM'.
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pub(crate) imem_phys_base: u32,
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/// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
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/// segments).
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pub(crate) imem_load_size: u32,
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/// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
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pub(crate) imem_virt_base: u32,
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/// Virtual address of secure IMEM segment.
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pub(crate) imem_sec_base: u32,
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/// Size of secure IMEM segment.
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pub(crate) imem_sec_size: u32,
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/// Offset into stored (uncompressed) image at which DMEM begins.
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pub(crate) dmem_offset: u32,
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/// Base address at which to load the data segment into 'DMEM'.
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pub(crate) dmem_phys_base: u32,
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/// Size in bytes of the data to copy into 'DMEM'.
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pub(crate) dmem_load_size: u32,
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/// "Alternate" Size of data to load into IMEM.
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pub(crate) alt_imem_load_size: u32,
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/// "Alternate" Size of data to load into DMEM.
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pub(crate) alt_dmem_load_size: u32,
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}
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/// Structure used to describe some firmwares, notably FWSEC-FRTS.
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#[repr(C)]
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#[derive(Debug, Clone)]
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pub(crate) struct FalconUCodeDescV3 {
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/// Header defined by `NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC*` in OpenRM.
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hdr: u32,
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/// Stored size of the ucode after the header.
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stored_size: u32,
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/// Offset in `DMEM` at which the signature is expected to be found.
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pub(crate) pkc_data_offset: u32,
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/// Offset after the code segment at which the app headers are located.
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pub(crate) interface_offset: u32,
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/// Base address at which to load the code segment into `IMEM`.
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pub(crate) imem_phys_base: u32,
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/// Size in bytes of the code to copy into `IMEM`.
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pub(crate) imem_load_size: u32,
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/// Virtual `IMEM` address (i.e. `tag`) at which the code should start.
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pub(crate) imem_virt_base: u32,
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/// Base address at which to load the data segment into `DMEM`.
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pub(crate) dmem_phys_base: u32,
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/// Size in bytes of the data to copy into `DMEM`.
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pub(crate) dmem_load_size: u32,
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/// Mask of the falcon engines on which this firmware can run.
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pub(crate) engine_id_mask: u16,
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/// ID of the ucode used to infer a fuse register to validate the signature.
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pub(crate) ucode_id: u8,
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/// Number of signatures in this firmware.
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pub(crate) signature_count: u8,
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/// Versions of the signatures, used to infer a valid signature to use.
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pub(crate) signature_versions: u16,
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_reserved: u16,
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}
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// SAFETY: all bit patterns are valid for this type, and it doesn't use
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// interior mutability.
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unsafe impl FromBytes for FalconUCodeDescV3 {}
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/// Enum wrapping the different versions of Falcon microcode descriptors.
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///
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/// This allows handling both V2 and V3 descriptor formats through a
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/// unified type, providing version-agnostic access to firmware metadata
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/// via the [`FalconUCodeDescriptor`] trait.
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#[derive(Debug, Clone)]
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pub(crate) enum FalconUCodeDesc {
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V2(FalconUCodeDescV2),
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V3(FalconUCodeDescV3),
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}
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impl Deref for FalconUCodeDesc {
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type Target = dyn FalconUCodeDescriptor;
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fn deref(&self) -> &Self::Target {
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match self {
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FalconUCodeDesc::V2(v2) => v2,
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FalconUCodeDesc::V3(v3) => v3,
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}
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}
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}
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/// Trait providing a common interface for accessing Falcon microcode descriptor fields.
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///
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/// This trait abstracts over the different descriptor versions ([`FalconUCodeDescV2`] and
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/// [`FalconUCodeDescV3`]), allowing code to work with firmware metadata without needing to
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/// know the specific descriptor version. Fields not present return zero.
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pub(crate) trait FalconUCodeDescriptor {
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fn hdr(&self) -> u32;
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fn imem_load_size(&self) -> u32;
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fn interface_offset(&self) -> u32;
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fn dmem_load_size(&self) -> u32;
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fn pkc_data_offset(&self) -> u32;
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fn engine_id_mask(&self) -> u16;
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fn ucode_id(&self) -> u8;
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fn signature_count(&self) -> u8;
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fn signature_versions(&self) -> u16;
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/// Returns the size in bytes of the header.
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fn size(&self) -> usize {
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let hdr = self.hdr();
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const HDR_SIZE_SHIFT: u32 = 16;
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const HDR_SIZE_MASK: u32 = 0xffff0000;
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((hdr & HDR_SIZE_MASK) >> HDR_SIZE_SHIFT).into_safe_cast()
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}
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fn imem_sec_load_params(&self) -> FalconDmaLoadTarget;
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fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget>;
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fn dmem_load_params(&self) -> FalconDmaLoadTarget;
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}
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impl FalconUCodeDescriptor for FalconUCodeDescV2 {
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fn hdr(&self) -> u32 {
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self.hdr
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}
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fn imem_load_size(&self) -> u32 {
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self.imem_load_size
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}
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fn interface_offset(&self) -> u32 {
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self.interface_offset
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}
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fn dmem_load_size(&self) -> u32 {
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self.dmem_load_size
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}
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fn pkc_data_offset(&self) -> u32 {
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0
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}
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fn engine_id_mask(&self) -> u16 {
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0
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}
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fn ucode_id(&self) -> u8 {
|
|
0
|
|
}
|
|
fn signature_count(&self) -> u8 {
|
|
0
|
|
}
|
|
fn signature_versions(&self) -> u16 {
|
|
0
|
|
}
|
|
|
|
fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
|
|
// `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
|
|
// `imem_virt_base` to get its physical offset.
|
|
let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
|
|
|
|
FalconDmaLoadTarget {
|
|
src_start: imem_sec_start,
|
|
dst_start: self.imem_phys_base.saturating_add(imem_sec_start),
|
|
len: self.imem_sec_size,
|
|
}
|
|
}
|
|
|
|
fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
|
|
Some(FalconDmaLoadTarget {
|
|
// Non-secure code always starts at offset 0.
|
|
src_start: 0,
|
|
dst_start: self.imem_phys_base,
|
|
// `imem_load_size` includes the size of the secure segment, so subtract it to
|
|
// get the correct amount of data to copy.
|
|
len: self.imem_load_size.saturating_sub(self.imem_sec_size),
|
|
})
|
|
}
|
|
|
|
fn dmem_load_params(&self) -> FalconDmaLoadTarget {
|
|
FalconDmaLoadTarget {
|
|
src_start: self.dmem_offset,
|
|
dst_start: self.dmem_phys_base,
|
|
len: self.dmem_load_size,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl FalconUCodeDescriptor for FalconUCodeDescV3 {
|
|
fn hdr(&self) -> u32 {
|
|
self.hdr
|
|
}
|
|
fn imem_load_size(&self) -> u32 {
|
|
self.imem_load_size
|
|
}
|
|
fn interface_offset(&self) -> u32 {
|
|
self.interface_offset
|
|
}
|
|
fn dmem_load_size(&self) -> u32 {
|
|
self.dmem_load_size
|
|
}
|
|
fn pkc_data_offset(&self) -> u32 {
|
|
self.pkc_data_offset
|
|
}
|
|
fn engine_id_mask(&self) -> u16 {
|
|
self.engine_id_mask
|
|
}
|
|
fn ucode_id(&self) -> u8 {
|
|
self.ucode_id
|
|
}
|
|
fn signature_count(&self) -> u8 {
|
|
self.signature_count
|
|
}
|
|
fn signature_versions(&self) -> u16 {
|
|
self.signature_versions
|
|
}
|
|
|
|
fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
|
|
FalconDmaLoadTarget {
|
|
// IMEM segment always starts at offset 0.
|
|
src_start: 0,
|
|
dst_start: self.imem_phys_base,
|
|
len: self.imem_load_size,
|
|
}
|
|
}
|
|
|
|
fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
|
|
// Not used on V3 platforms
|
|
None
|
|
}
|
|
|
|
fn dmem_load_params(&self) -> FalconDmaLoadTarget {
|
|
FalconDmaLoadTarget {
|
|
// DMEM segment starts right after the IMEM one.
|
|
src_start: self.imem_load_size,
|
|
dst_start: self.dmem_phys_base,
|
|
len: self.dmem_load_size,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Trait implemented by types defining the signed state of a firmware.
|
|
trait SignedState {}
|
|
|
|
/// Type indicating that the firmware must be signed before it can be used.
|
|
struct Unsigned;
|
|
impl SignedState for Unsigned {}
|
|
|
|
/// Type indicating that the firmware is signed and ready to be loaded.
|
|
struct Signed;
|
|
impl SignedState for Signed {}
|
|
|
|
/// Microcode to be loaded into a specific falcon.
|
|
///
|
|
/// This is module-local and meant for sub-modules to use internally.
|
|
///
|
|
/// After construction, a firmware is [`Unsigned`], and must generally be patched with a signature
|
|
/// before it can be loaded (with an exception for development hardware). The
|
|
/// [`Self::patch_signature`] and [`Self::no_patch_signature`] methods are used to transition the
|
|
/// firmware to its [`Signed`] state.
|
|
// TODO: Consider replacing this with a coherent memory object once `CoherentAllocation` supports
|
|
// temporary CPU-exclusive access to the object without unsafe methods.
|
|
struct FirmwareObject<F: FalconFirmware, S: SignedState>(KVVec<u8>, PhantomData<(F, S)>);
|
|
|
|
/// Trait for signatures to be patched directly into a given firmware.
|
|
///
|
|
/// This is module-local and meant for sub-modules to use internally.
|
|
trait FirmwareSignature<F: FalconFirmware>: AsRef<[u8]> {}
|
|
|
|
impl<F: FalconFirmware> FirmwareObject<F, Unsigned> {
|
|
/// Patches the firmware at offset `signature_start` with `signature`.
|
|
fn patch_signature<S: FirmwareSignature<F>>(
|
|
mut self,
|
|
signature: &S,
|
|
signature_start: usize,
|
|
) -> Result<FirmwareObject<F, Signed>> {
|
|
let signature_bytes = signature.as_ref();
|
|
let signature_end = signature_start
|
|
.checked_add(signature_bytes.len())
|
|
.ok_or(EOVERFLOW)?;
|
|
let dst = self
|
|
.0
|
|
.get_mut(signature_start..signature_end)
|
|
.ok_or(EINVAL)?;
|
|
|
|
// PANIC: `dst` and `signature_bytes` have the same length.
|
|
dst.copy_from_slice(signature_bytes);
|
|
|
|
Ok(FirmwareObject(self.0, PhantomData))
|
|
}
|
|
|
|
/// Mark the firmware as signed without patching it.
|
|
///
|
|
/// This method is used to explicitly confirm that we do not need to sign the firmware, while
|
|
/// allowing us to continue as if it was. This is typically only needed for development
|
|
/// hardware.
|
|
fn no_patch_signature(self) -> FirmwareObject<F, Signed> {
|
|
FirmwareObject(self.0, PhantomData)
|
|
}
|
|
}
|
|
|
|
/// Header common to most firmware files.
|
|
#[repr(C)]
|
|
#[derive(Debug, Clone)]
|
|
struct BinHdr {
|
|
/// Magic number, must be `0x10de`.
|
|
bin_magic: u32,
|
|
/// Version of the header.
|
|
bin_ver: u32,
|
|
/// Size in bytes of the binary (to be ignored).
|
|
bin_size: u32,
|
|
/// Offset of the start of the application-specific header.
|
|
header_offset: u32,
|
|
/// Offset of the start of the data payload.
|
|
data_offset: u32,
|
|
/// Size in bytes of the data payload.
|
|
data_size: u32,
|
|
}
|
|
|
|
// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
|
|
unsafe impl FromBytes for BinHdr {}
|
|
|
|
// A firmware blob starting with a `BinHdr`.
|
|
struct BinFirmware<'a> {
|
|
hdr: BinHdr,
|
|
fw: &'a [u8],
|
|
}
|
|
|
|
impl<'a> BinFirmware<'a> {
|
|
/// Interpret `fw` as a firmware image starting with a [`BinHdr`], and returns the
|
|
/// corresponding [`BinFirmware`] that can be used to extract its payload.
|
|
fn new(fw: &'a firmware::Firmware) -> Result<Self> {
|
|
const BIN_MAGIC: u32 = 0x10de;
|
|
let fw = fw.data();
|
|
|
|
fw.get(0..size_of::<BinHdr>())
|
|
// Extract header.
|
|
.and_then(BinHdr::from_bytes_copy)
|
|
// Validate header.
|
|
.filter(|hdr| hdr.bin_magic == BIN_MAGIC)
|
|
.map(|hdr| Self { hdr, fw })
|
|
.ok_or(EINVAL)
|
|
}
|
|
|
|
/// Returns the data payload of the firmware, or `None` if the data range is out of bounds of
|
|
/// the firmware image.
|
|
fn data(&self) -> Option<&[u8]> {
|
|
let fw_start = usize::from_safe_cast(self.hdr.data_offset);
|
|
let fw_size = usize::from_safe_cast(self.hdr.data_size);
|
|
let fw_end = fw_start.checked_add(fw_size)?;
|
|
|
|
self.fw.get(fw_start..fw_end)
|
|
}
|
|
}
|
|
|
|
pub(crate) struct ModInfoBuilder<const N: usize>(firmware::ModInfoBuilder<N>);
|
|
|
|
impl<const N: usize> ModInfoBuilder<N> {
|
|
const fn make_entry_file(self, chipset: &str, fw: &str) -> Self {
|
|
ModInfoBuilder(
|
|
self.0
|
|
.new_entry()
|
|
.push("nvidia/")
|
|
.push(chipset)
|
|
.push("/gsp/")
|
|
.push(fw)
|
|
.push("-")
|
|
.push(FIRMWARE_VERSION)
|
|
.push(".bin"),
|
|
)
|
|
}
|
|
|
|
const fn make_entry_chipset(self, chipset: gpu::Chipset) -> Self {
|
|
let name = chipset.name();
|
|
|
|
let this = self
|
|
.make_entry_file(name, "booter_load")
|
|
.make_entry_file(name, "booter_unload")
|
|
.make_entry_file(name, "bootloader")
|
|
.make_entry_file(name, "gsp");
|
|
|
|
let this = if chipset.needs_fwsec_bootloader() {
|
|
this.make_entry_file(name, "gen_bootloader")
|
|
} else {
|
|
this
|
|
};
|
|
|
|
if chipset.uses_fsp() {
|
|
this.make_entry_file(name, "fmc")
|
|
} else {
|
|
this
|
|
}
|
|
}
|
|
|
|
pub(crate) const fn create(
|
|
module_name: &'static core::ffi::CStr,
|
|
) -> firmware::ModInfoBuilder<N> {
|
|
let mut this = Self(firmware::ModInfoBuilder::new(module_name));
|
|
let mut i = 0;
|
|
|
|
while i < gpu::Chipset::ALL.len() {
|
|
this = this.make_entry_chipset(gpu::Chipset::ALL[i]);
|
|
i += 1;
|
|
}
|
|
|
|
this.0
|
|
}
|
|
}
|
|
|
|
/// Ad-hoc and temporary module to extract sections from ELF images.
|
|
///
|
|
/// Some firmware images are currently packaged as ELF files, where sections names are used as keys
|
|
/// to specific and related bits of data. Future firmware versions are scheduled to move away from
|
|
/// that scheme before nova-core becomes stable, which means this module will eventually be
|
|
/// removed.
|
|
mod elf {
|
|
use core::mem::size_of;
|
|
|
|
use kernel::{
|
|
bindings,
|
|
str::CStr,
|
|
transmute::FromBytes, //
|
|
};
|
|
|
|
/// Trait to abstract over ELF header differences.
|
|
trait ElfHeader: FromBytes {
|
|
fn shnum(&self) -> u16;
|
|
fn shoff(&self) -> u64;
|
|
fn shstrndx(&self) -> u16;
|
|
}
|
|
|
|
/// Trait to abstract over ELF section-header differences.
|
|
trait ElfSectionHeader: FromBytes {
|
|
fn name(&self) -> u32;
|
|
fn offset(&self) -> u64;
|
|
fn size(&self) -> u64;
|
|
}
|
|
|
|
/// Trait describing a matching ELF header and section-header format.
|
|
trait ElfFormat {
|
|
type Header: ElfHeader;
|
|
type SectionHeader: ElfSectionHeader;
|
|
}
|
|
|
|
/// Newtype to provide a [`FromBytes`] implementation.
|
|
#[repr(transparent)]
|
|
struct Elf64Hdr(bindings::elf64_hdr);
|
|
// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
|
|
unsafe impl FromBytes for Elf64Hdr {}
|
|
|
|
impl ElfHeader for Elf64Hdr {
|
|
fn shnum(&self) -> u16 {
|
|
self.0.e_shnum
|
|
}
|
|
|
|
fn shoff(&self) -> u64 {
|
|
self.0.e_shoff
|
|
}
|
|
|
|
fn shstrndx(&self) -> u16 {
|
|
self.0.e_shstrndx
|
|
}
|
|
}
|
|
|
|
#[repr(transparent)]
|
|
struct Elf64SHdr(bindings::elf64_shdr);
|
|
// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
|
|
unsafe impl FromBytes for Elf64SHdr {}
|
|
|
|
impl ElfSectionHeader for Elf64SHdr {
|
|
fn name(&self) -> u32 {
|
|
self.0.sh_name
|
|
}
|
|
|
|
fn offset(&self) -> u64 {
|
|
self.0.sh_offset
|
|
}
|
|
|
|
fn size(&self) -> u64 {
|
|
self.0.sh_size
|
|
}
|
|
}
|
|
|
|
struct Elf64Format;
|
|
|
|
impl ElfFormat for Elf64Format {
|
|
type Header = Elf64Hdr;
|
|
type SectionHeader = Elf64SHdr;
|
|
}
|
|
|
|
/// Newtype to provide [`FromBytes`] and [`ElfHeader`] implementations for ELF32.
|
|
#[repr(transparent)]
|
|
struct Elf32Hdr(bindings::elf32_hdr);
|
|
// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
|
|
unsafe impl FromBytes for Elf32Hdr {}
|
|
|
|
impl ElfHeader for Elf32Hdr {
|
|
fn shnum(&self) -> u16 {
|
|
self.0.e_shnum
|
|
}
|
|
|
|
fn shoff(&self) -> u64 {
|
|
u64::from(self.0.e_shoff)
|
|
}
|
|
|
|
fn shstrndx(&self) -> u16 {
|
|
self.0.e_shstrndx
|
|
}
|
|
}
|
|
|
|
/// Newtype to provide [`FromBytes`] and [`ElfSectionHeader`] implementations for ELF32.
|
|
#[repr(transparent)]
|
|
struct Elf32SHdr(bindings::elf32_shdr);
|
|
// SAFETY: all bit patterns are valid for this type, and it doesn't use interior mutability.
|
|
unsafe impl FromBytes for Elf32SHdr {}
|
|
|
|
impl ElfSectionHeader for Elf32SHdr {
|
|
fn name(&self) -> u32 {
|
|
self.0.sh_name
|
|
}
|
|
|
|
fn offset(&self) -> u64 {
|
|
u64::from(self.0.sh_offset)
|
|
}
|
|
|
|
fn size(&self) -> u64 {
|
|
u64::from(self.0.sh_size)
|
|
}
|
|
}
|
|
|
|
struct Elf32Format;
|
|
|
|
impl ElfFormat for Elf32Format {
|
|
type Header = Elf32Hdr;
|
|
type SectionHeader = Elf32SHdr;
|
|
}
|
|
|
|
/// Returns a NULL-terminated string from the ELF image at `offset`.
|
|
fn elf_str(elf: &[u8], offset: u64) -> Option<&str> {
|
|
let idx = usize::try_from(offset).ok()?;
|
|
let bytes = elf.get(idx..)?;
|
|
CStr::from_bytes_until_nul(bytes).ok()?.to_str().ok()
|
|
}
|
|
|
|
fn elf_section_generic<'a, F>(elf: &'a [u8], name: &str) -> Option<&'a [u8]>
|
|
where
|
|
F: ElfFormat,
|
|
{
|
|
let hdr = F::Header::from_bytes(elf.get(0..size_of::<F::Header>())?)?;
|
|
|
|
let shdr_num = usize::from(hdr.shnum());
|
|
let shdr_start = usize::try_from(hdr.shoff()).ok()?;
|
|
let shdr_end = shdr_num
|
|
.checked_mul(size_of::<F::SectionHeader>())
|
|
.and_then(|v| v.checked_add(shdr_start))?;
|
|
|
|
// Get all the section headers as an iterator over byte chunks.
|
|
let shdr_bytes = elf.get(shdr_start..shdr_end)?;
|
|
let mut shdr_iter = shdr_bytes.chunks_exact(size_of::<F::SectionHeader>());
|
|
|
|
// Get the strings table.
|
|
let strhdr = shdr_iter
|
|
.clone()
|
|
.nth(usize::from(hdr.shstrndx()))
|
|
.and_then(F::SectionHeader::from_bytes)?;
|
|
|
|
// Find the section which name matches `name` and return it.
|
|
shdr_iter.find_map(|sh_bytes| {
|
|
let sh = F::SectionHeader::from_bytes(sh_bytes)?;
|
|
let name_offset = strhdr.offset().checked_add(u64::from(sh.name()))?;
|
|
let section_name = elf_str(elf, name_offset)?;
|
|
|
|
if section_name != name {
|
|
return None;
|
|
}
|
|
|
|
let start = usize::try_from(sh.offset()).ok()?;
|
|
let end = usize::try_from(sh.size())
|
|
.ok()
|
|
.and_then(|sz| start.checked_add(sz))?;
|
|
|
|
elf.get(start..end)
|
|
})
|
|
}
|
|
|
|
/// Extract the section with name `name` from the ELF64 image `elf`.
|
|
fn elf64_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
|
|
elf_section_generic::<Elf64Format>(elf, name)
|
|
}
|
|
|
|
/// Extract the section with name `name` from the ELF32 image `elf`.
|
|
fn elf32_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
|
|
elf_section_generic::<Elf32Format>(elf, name)
|
|
}
|
|
|
|
/// Automatically detects ELF32 vs ELF64 based on the ELF header.
|
|
pub(super) fn elf_section<'a>(elf: &'a [u8], name: &str) -> Option<&'a [u8]> {
|
|
// ELF identification: a 4-byte magic followed by a class byte (32- vs 64-bit).
|
|
const ELFMAG: &[u8] = b"\x7fELF";
|
|
const SELFMAG: usize = ELFMAG.len();
|
|
const EI_CLASS: usize = 4;
|
|
const ELFCLASS32: u8 = 1;
|
|
const ELFCLASS64: u8 = 2;
|
|
|
|
if elf.get(0..SELFMAG) != Some(ELFMAG) {
|
|
return None;
|
|
}
|
|
|
|
match *elf.get(EI_CLASS)? {
|
|
ELFCLASS32 => elf32_section(elf, name),
|
|
ELFCLASS64 => elf64_section(elf, name),
|
|
_ => None,
|
|
}
|
|
}
|
|
}
|