Saaem Rizvi 2da3556c86 drm/amd/display: Trigger DIO FIFO resync on commit streams for DCN32 ... [WHY and HOW] Currently, on DCN32 we have an old workaround to resolve a DIO FIFO speed issue when writing to the OTG DIVIDER register. However, this workaround is not safe as we should be applying the DIO FIFO rampup logic when the OTG re disabled along with the encoders. This new workaround accounts for this. If the workaround sequence is incorrect, like it is was, there is a chance we might hang. this new workaround was first implemented in DCN314. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-06-09 10:44:17 -04:00
..
amdgpu_dm	drm/amd/display: Have Payload Properly Created After Resume	2023-06-09 10:42:51 -04:00
dc	drm/amd/display: Trigger DIO FIFO resync on commit streams for DCN32	2023-06-09 10:44:17 -04:00
dmub	drm/amd/display: Update correct DCN314 register header	2023-06-09 10:44:14 -04:00
include	drm/amd/display: Convert connector signal id to string	2023-06-09 09:39:41 -04:00
modules	drm/amd/display: set variable custom_backlight_curve0 storage-class-specifier to static	2023-06-09 09:23:18 -04:00
Kconfig	drm/amdgpu/display: Enable DC_FP for LoongArch	2023-06-09 09:36:48 -04:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP	2023-03-07 14:22:39 -05:00
TODO