Andy Shevchenko 49c0309626 pinctrl: baytrail: Do not add all GPIOs to IRQ domain ... When DIRECT_IRQ_EN is set, the pin is routed directly to the IO-APIC bypassing the GPIO driver completely. However, the mask register is still used to determine if the pin is supposed to generate IRQ or not. So with commit 3ae02c14d9 the IRQ core masks all IRQs (because of handle_bad_irq()) the pin connected to the touchscreen gets masked as well and hence no interrupts. To make this all work as expected we do not add those GPIOs to the IRQ domain that can actually propagate interrupts. Fixes: 3ae02c14d9 ("pinctrl: intel: set default handler to be handle_bad_irq()") Reported-by: Robert R. Howell <rhowell@uwyo.edu> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2017-01-12 08:11:56 +01:00
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Kconfig	pinctrl: intel: Add Intel Merrifield pin controller support	2016-06-29 09:59:35 +02:00
Makefile	pinctrl: intel: Add Intel Merrifield pin controller support	2016-06-29 09:59:35 +02:00
pinctrl-baytrail.c	pinctrl: baytrail: Do not add all GPIOs to IRQ domain	2017-01-12 08:11:56 +01:00
pinctrl-broxton.c	pinctrl: broxton: Use correct PADCFGLOCK offset	2017-01-11 13:47:11 +01:00
pinctrl-cherryview.c	Bulk pin control changes for the v4.10 kernel cycle:	2016-12-13 07:59:10 -08:00
pinctrl-intel.c	pinctrl: intel: Set pin direction properly	2017-01-11 13:49:05 +01:00
pinctrl-intel.h	pinctrl: intel: fix bug of register offset calculation	2015-12-10 23:01:41 +01:00
pinctrl-merrifield.c	pinctrl: intel: merrifield: Add pin config group handlers	2016-10-29 10:33:47 +02:00
pinctrl-sunrisepoint.c	pinctrl: intel: fix bug of register offset calculation	2015-12-10 23:01:41 +01:00