Alvin Lee 196754951f drm/amd/display: Block SubVP + DRR if the DRR is PSR capable ... [Description] PSR implementation in FW has inline polling which can poll for up to 1ms. This will interfere with SubVP because SubVP is timing sensitive and can't tolerate up to 1ms worth of delay before handling vertical or VLINE interrupts. Therefore block SubVP + DRR cases if DRR is PSR capable Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-06-15 10:44:39 -04:00
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amdgpu_dm	drm/amd/display: fix the system hang while disable PSR	2023-06-15 10:44:19 -04:00
dc	drm/amd/display: Block SubVP + DRR if the DRR is PSR capable	2023-06-15 10:44:39 -04:00
dmub	Revert "drm/amd/display: cache trace buffer size"	2023-06-09 12:50:08 -04:00
include	drm/amd/display: fix compilation error due to shifting negative value	2023-06-09 12:38:19 -04:00
modules	drm/amd/display: set variable custom_backlight_curve0 storage-class-specifier to static	2023-06-09 09:23:18 -04:00
Kconfig	Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next	2023-06-15 14:11:22 +10:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP	2023-03-07 14:22:39 -05:00
TODO