Krishna Chaitanya Chundru 178af54a67 PCI: Add lane equalization register offsets ... As per PCIe spec 6.0.1, add PCIe lane equalization register offset for data rates 8.0 GT/s, 32.0 GT/s and 64.0 GT/s. Also add a macro for defining data rate 64.0 GT/s physical layer capability ID. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250328-preset_v6-v9-4-22cfa0490518@oss.qualcomm.com		2025-04-19 19:42:43 +05:30
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asm-generic	arm64 updates for 6.15:	2025-03-25 13:16:16 -07:00
cxl	cxl: Add support for fwctl RPC command to enable CXL feature commands	2025-03-17 14:41:37 -03:00
drm	drm/xe/uapi: Add DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	2025-03-06 11:35:52 -08:00
fwctl	pds_fwctl: add rpc and query support	2025-03-21 20:57:55 -03:00
linux	PCI: Add lane equalization register offsets	2025-04-19 19:42:43 +05:30
misc	cxl: Remove driver	2025-03-16 22:04:27 +11:00
mtd	ubi: Expose interface for detailed erase counters	2025-01-18 15:32:32 +01:00
rdma	RDMA/core: Add support to optional-counters binding configuration	2025-03-18 06:18:42 -04:00
regulator	uapi: regulator: Fix typo	2024-01-04 13:22:24 +00:00
scsi	scsi: cxlflash: Remove driver	2025-02-03 18:04:55 -05:00
sound	ASoC: Intel: avs: Make PEAKVOL configurable from topology	2025-02-24 16:01:53 +00:00
video
xen	xen/privcmd: Add new syscall to get gsi from dev	2024-09-25 09:54:55 +02:00
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