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This commits adds a new irqchip driver that handles the ODMI controller found on Marvell 7K/8K processors. The ODMI controller provide MSI interrupt functionality to on-board peripherals, much like the GIC-v2m. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
42 lines
1.4 KiB
Plaintext
42 lines
1.4 KiB
Plaintext
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* Marvell ODMI for MSI support
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Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
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which can be used by on-board peripheral for MSI interrupts.
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Required properties:
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- compatible : The value here should contain "marvell,odmi-controller".
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- interrupt,controller : Identifies the node as an interrupt controller.
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- msi-controller : Identifies the node as an MSI controller.
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- marvell,odmi-frames : Number of ODMI frames available. Each frame
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provides a number of events.
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- reg : List of register definitions, one for each
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ODMI frame.
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- marvell,spi-base : List of GIC base SPI interrupts, one for each
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ODMI frame. Those SPI interrupts are 0-based,
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i.e marvell,spi-base = <128> will use SPI #96.
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See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
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for details about the GIC Device Tree binding.
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- interrupt-parent : Reference to the parent interrupt controller.
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Example:
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odmi: odmi@300000 {
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compatible = "marvell,odmi-controller";
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interrupt-controller;
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msi-controller;
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marvell,odmi-frames = <4>;
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reg = <0x300000 0x4000>,
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<0x304000 0x4000>,
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<0x308000 0x4000>,
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<0x30C000 0x4000>;
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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