mirror of
https://github.com/torvalds/linux.git
synced 2026-06-08 22:52:35 +02:00
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connection. This patch select the pipe to the corresponding
controller when set phy mode.
+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+
+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+
Change-Id: I6ec6dd0a0202119633e594c9a72f361156330b06
Signed-off-by: William Wu <william.wu@rock-chips.com>
|
||
|---|---|---|
| .. | ||
| allwinner | ||
| amlogic | ||
| broadcom | ||
| hisilicon | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| motorola | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| st | ||
| tegra | ||
| ti | ||
| Kconfig | ||
| Makefile | ||
| phy-core.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||