George Shen 12f72a1599 drm/amd/display: Add DP audio BW validation ... [Why] Timings with small HBlank (such as CVT RBv2) can result in insufficient HBlank bandwidth for audio SDP transmission when DSC is active. This will cause some higher bandwidth audio modes to fail. The combination of CVT RBv2 timings + DSC can commonly be encountered in MST scenarios. [How] Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST cases and filter out modes that cannot be supported with the current timing config. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-01-15 18:35:39 -05:00
..
amdgpu_dm	drm/amd/display: Allow IPS2 during Replay	2024-01-15 18:35:37 -05:00
dc	drm/amd/display: Add DP audio BW validation	2024-01-15 18:35:39 -05:00
dmub	drm/amd/display: Add Replay IPS register for DMUB command table	2024-01-15 18:35:37 -05:00
include	drm/amd/display: Add DP audio BW validation	2024-01-15 18:35:39 -05:00
modules	drm/amd/display: Fix power_helpers.c codestyle	2024-01-05 16:10:44 -05:00
Kconfig	drm/amd/display: Allow building DC with clang on RISC-V	2023-07-21 16:52:25 -04:00
Makefile	drm/amd/display: Refactor OPTC into component folder	2023-11-29 16:49:01 -05:00
TODO