Xixin Liu 6809da6e9c perf: RISC-V: store available counter mask as bitmap ... The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong. Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough. Fixes: e999143459 ("RISC-V: Add perf platform driver based on SBI PMU extension") Assisted-by: DeepSeek:deepseek-v3 Signed-off-by: Xixin Liu <liuxixin@kylinos.cn> Link: https://patch.msgid.link/prpmask02cmap.v2.1786434000.git.liuxixin@kylinos.cn Cc: stable@kernel.org [pjw@kernel.org: updated to apply; fixed checkpatch.pl issues] Signed-off-by: Paul Walmsley <pjw@kernel.org>		2026-09-01 19:19:26 -06:00
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arm_pmu.h	perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus	2026-07-21 21:40:35 +00:00
arm_pmuv3.h	perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control	2024-10-28 17:27:15 +00:00
riscv_pmu.h	perf: RISC-V: store available counter mask as bitmap	2026-09-01 19:19:26 -06:00