Kever Yang 39e58a61a5 phy: phy-rockchip-snps-pcie3: Add pcie3_phymode setting ... rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four lanes, add support in dts so that we can customize in dts. The phy has two port and each port has two lane: pcie30_phy_mode[2:0] 2: aggregation 1: bifurcation for port 1 0: bifurcation for port 0 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I0546329cc53df05f0779a7b34d948158bbc5ebcd		2021-11-16 16:23:36 +08:00
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phy-am654-serdes.h	dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC	2019-04-17 14:13:18 +05:30
phy-cadence-torrent.h	dt-bindings: phy: cadence-torrent: Add binding to specify SSC mode	2020-09-18 10:34:48 +05:30
phy-lantiq-vrx200-pcie.h	dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs	2019-08-23 09:40:46 +05:30
phy-ocelot-serdes.h	dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1	2018-10-22 19:27:14 -07:00
phy-pistachio-usb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
phy-qcom-qusb2.h	dt-bindings: phy-qcom-usb2: Add support to override tuning values	2018-05-20 21:51:31 +05:30
phy-snps-pcie3.h	phy: phy-rockchip-snps-pcie3: Add pcie3_phymode setting	2021-11-16 16:23:36 +08:00
phy.h	dt-bindings: phy: Add PHY_TYPE_QSGMII definition	2020-09-18 10:47:19 +05:30