Sugar Zhang d27ca5b359 drm/bridge: synopsys: dw-hdmi-qp: Fix audio infoframe ... AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } PB0: CheckSum PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | PB6~PB10: Reserved AUDI_CONTENTS0 default value defined by HDMI specification, and shall only be changed for debug purposes. So, we only configure payload byte from PB0~PB7(2 word total). Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: Idfbb34ff7f7069af4e73c6995f32eefa798a9450		2022-03-12 16:29:28 +08:00
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analogix_dp.h	drm/bridge: analogix_dp: Rework irq handling	2022-02-22 14:53:17 +08:00
dw_hdmi.h	drm/bridge: synopsys: dw-hdmi-qp: Fix audio infoframe	2022-03-12 16:29:28 +08:00
dw_mipi_dsi.h	drm/bridge: dw-mipi-dsi: remove the pclk which can be managed in runtime pm	2021-09-03 17:48:03 +08:00
mhl.h	drm/bridge/mhl.h: Replace zero-length array with flexible-array member	2020-03-06 11:52:01 +01:00