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Grzegorz Nitka says: ==================== dpll/ice: Add generic DPLL type and full TX reference clock control for E825 NOTE: This series is intentionally submitted on net-next (not intel-wired-lan) as early feedback of DPLL subsystem changes is welcomed. In the past possible approaches were discussed in [1]. This series adds TX reference clock support for E825 devices and exposes TX clock selection and synchronization status via the Linux DPLL subsystem. Here is the high-level connection diagram for E825 device: +------------------------------------------------------------------+ | | | +-----------------------------+ | | | | | | | MAC | | | |+------------+-----+ | | | ||RX/1588 |PHC|tspll<----\ | | +---+----+ ||MUX +---+-^---| | | | | E | RX >---------------------> | >--\ | | | | T | | /----------------> | >-\| | | | | H |----+ | |+---------+----^---+ || | | | | 1 | TX <----|----------------+TX MUX < OCXO | || | | | | |PLL | | || |--------| || | | | +---+----+ | /----+ <-ext_ref<-||-|----|------ext_ref | E | RX >----/ | || |--------+ || | | | | T | | | || < SyncE | || | | | | H |----+ | |+-----------^------+ || | | | | 2 | TX <----------------/ | | /------||-/ | | | |PLL | +------------|-|------||------+ | +---+----+ /--/ | || | | . | RX >--- | | || | | . | | +----------|----|------||--+ | | . |----+ | +-^-+--^+ || | | | | TX <--- | |EEC|PPS| || | | | |PLL | | +-------+ || | | +---+----+ | | <-CLK0/| | | | E | RX >--- | | DPLL | | | | | T | | | | <-CLK1-/ | | | H |----+ | | | | | | X | TX <--- | | <---SMA---< | | |PLL | | | | | | +---+----+ | | <---GPS---< | | | | | | | | | | <---...---< | | | | | | | | | +-------+ | | | | External timing module | | | +--------------------------+ | +------------------------------------------------------------------+ E825 hardware contains a dedicated TX clock domain with per-port source selection behavior that is distinct from PPS handling and from board-level EEC distribution. TX reference clock selection is device-wide, shared across ports, and mediated by firmware as part of link bring-up. As a result, TX clock selection intent may differ from effective hardware configuration, and software must verify outcome after link-up. To support this, the series extends the DPLL core and the ice driver incrementally. The series also introduces DPLL_TYPE_GENERIC as a broad UAPI class for DPLL instances outside PPS/EEC categories. The intent is to keep type naming reusable and scalable across different ASIC topologies while preserving functional discoverability via driver/device context and pin topology. This follows netdev discussion guidance that UAPI type naming should avoid location-specific or vendor-specific taxonomy, because such labels do not scale across different ASIC designs. The function of a given DPLL instance is already discoverable from driver/device context and pin topology, and does not require an additional narrow type identifier in UAPI. At the same time, a separate DPLL object is still needed for E825 TX clock control/reporting semantics. Using DPLL_TYPE_GENERIC provides a reusable class for devices outside PPS/EEC without overfitting UAPI naming to one topology. The relevant discussion is in [2]. Series content - add a new generic DPLL type for devices outside PPS/EEC classes; - relax DPLL pin registration rules for firmware-described shared pins and extend pin notifications with a source identifier; - allow dynamic state control of SyncE reference pins where hardware supports it; - add CPI infrastructure for PHY-side TX clock control on E825C; - introduce a TX-clock DPLL device and TX reference clock pins (EXT_EREF0 and SYNCE) in the ice driver; - extend the Restart Auto-Negotiation command to carry a TX reference clock index; - implement hardware-backed TX reference clock switching, post-link verification, and TX synchronization reporting. TXCLK pins report TX reference topology only. Actual synchronization success is reported via DPLL lock status, updated after hardware verification: external TX references report LOCKED, while the internal ENET/TXCO source reports UNLOCKED. This provides reliable TX reference selection and observability on E825 devices using standard DPLL interfaces, without conflating user intent with effective hardware behavior. [1] https://lore.kernel.org/netdev/20250905160333.715c34ac@kernel.org/ [2] https://lore.kernel.org/netdev/20260402230626.3826719-1-grzegorz.nitka@intel.com/ ==================== Link: https://patch.msgid.link/20260607183045.1213735-1-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
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