Biju Das 9a882c7737 dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder ... Document the LVDS encoder IP found on the RZ/G3L SoC. It supports single-link mode. LVDS and the DSI interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be used at the same time as MIPI-DSI. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260729125516.230757-10-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>		2026-08-05 14:08:35 +01:00
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bindings	dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder	2026-08-05 14:08:35 +01:00
changesets.rst
dynamic-resolution-notes.rst
index.rst
kernel-api.rst
of_unittest.rst	docs: dt: unittest: update to current unittest filenames	2026-02-24 14:59:12 -06:00
overlay-notes.rst
usage-model.rst