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0c3a877469
Use u32 instead of uint32_t to make the KVM selftests code more concise and more similar to the kernel (since selftests are primarily developed by kernel developers). This commit was generated with the following command: git ls-files tools/testing/selftests/kvm | xargs sed -i 's/uint32_t/u32/g' Then by manually adjusting whitespace to make checkpatch.pl happy. No functional change intended. Signed-off-by: David Matlack <dmatlack@google.com> Link: https://patch.msgid.link/20260420212004.3938325-7-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
164 lines
3.2 KiB
C
164 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Generic Interrupt Controller (GIC) support
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*/
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#include <errno.h>
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#include <linux/bits.h>
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#include <linux/sizes.h>
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#include "kvm_util.h"
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#include <gic.h>
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#include "gic_private.h"
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#include "processor.h"
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#include "spinlock.h"
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static const struct gic_common_ops *gic_common_ops;
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static struct spinlock gic_lock;
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static void gic_cpu_init(unsigned int cpu)
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{
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gic_common_ops->gic_cpu_init(cpu);
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}
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static void gic_dist_init(enum gic_type type, unsigned int nr_cpus)
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{
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const struct gic_common_ops *gic_ops = NULL;
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spin_lock(&gic_lock);
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/* Distributor initialization is needed only once per VM */
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if (gic_common_ops) {
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spin_unlock(&gic_lock);
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return;
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}
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if (type == GIC_V3)
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gic_ops = &gicv3_ops;
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GUEST_ASSERT(gic_ops);
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gic_ops->gic_init(nr_cpus);
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gic_common_ops = gic_ops;
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/* Make sure that the initialized data is visible to all the vCPUs */
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dsb(sy);
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spin_unlock(&gic_lock);
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}
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void gic_init(enum gic_type type, unsigned int nr_cpus)
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{
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u32 cpu = guest_get_vcpuid();
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GUEST_ASSERT(type < GIC_TYPE_MAX);
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GUEST_ASSERT(nr_cpus);
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gic_dist_init(type, nr_cpus);
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gic_cpu_init(cpu);
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}
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void gic_irq_enable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_enable(intid);
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}
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void gic_irq_disable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_disable(intid);
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}
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unsigned int gic_get_and_ack_irq(void)
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{
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u64 irqstat;
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unsigned int intid;
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GUEST_ASSERT(gic_common_ops);
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irqstat = gic_common_ops->gic_read_iar();
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intid = irqstat & GENMASK(23, 0);
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return intid;
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}
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void gic_set_eoi(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_write_eoir(intid);
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}
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void gic_set_dir(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_write_dir(intid);
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}
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void gic_set_eoi_split(bool split)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_eoi_split(split);
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}
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void gic_set_priority_mask(u64 pmr)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_priority_mask(pmr);
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}
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void gic_set_priority(unsigned int intid, unsigned int prio)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_set_priority(intid, prio);
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}
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void gic_irq_set_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_active(intid);
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}
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void gic_irq_clear_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_clear_active(intid);
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}
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bool gic_irq_get_active(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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return gic_common_ops->gic_irq_get_active(intid);
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}
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void gic_irq_set_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_pending(intid);
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}
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void gic_irq_clear_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_clear_pending(intid);
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}
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bool gic_irq_get_pending(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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return gic_common_ops->gic_irq_get_pending(intid);
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}
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void gic_irq_set_config(unsigned int intid, bool is_edge)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_config(intid, is_edge);
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}
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void gic_irq_set_group(unsigned int intid, bool group)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_set_group(intid, group);
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}
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