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e47b8e1db9
Extend the PMU test suite to cover overflow interrupts. The test enables the PMI (Performance Monitor Interrupt), sets counter 0 to one less than the overflow value, and verifies that an interrupt is raised when the counter overflows. A guest interrupt handler checks the interrupt cause and disables further PMU interrupts upon success. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* LoongArch PMU specific interface
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*/
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#ifndef SELFTEST_KVM_PMU_H
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#define SELFTEST_KVM_PMU_H
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#include "processor.h"
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#define LOONGARCH_CPUCFG6 0x6
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#define CPUCFG6_PMP BIT(0)
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#define CPUCFG6_PAMVER GENMASK(3, 1)
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#define CPUCFG6_PMNUM GENMASK(7, 4)
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#define CPUCFG6_PMNUM_SHIFT 4
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#define CPUCFG6_PMBITS GENMASK(13, 8)
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#define CPUCFG6_PMBITS_SHIFT 8
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#define CPUCFG6_UPM BIT(14)
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/* Performance Counter registers */
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#define LOONGARCH_CSR_PERFCTRL0 0x200 /* perf event 0 config */
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#define LOONGARCH_CSR_PERFCNTR0 0x201 /* perf event 0 count value */
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#define LOONGARCH_CSR_PERFCTRL1 0x202 /* perf event 1 config */
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#define LOONGARCH_CSR_PERFCNTR1 0x203 /* perf event 1 count value */
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#define LOONGARCH_CSR_PERFCTRL2 0x204 /* perf event 2 config */
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#define LOONGARCH_CSR_PERFCNTR2 0x205 /* perf event 2 count value */
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#define LOONGARCH_CSR_PERFCTRL3 0x206 /* perf event 3 config */
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#define LOONGARCH_CSR_PERFCNTR3 0x207 /* perf event 3 count value */
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#define CSR_PERFCTRL_PLV0 BIT(16)
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#define CSR_PERFCTRL_PLV1 BIT(17)
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#define CSR_PERFCTRL_PLV2 BIT(18)
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#define CSR_PERFCTRL_PLV3 BIT(19)
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#define CSR_PERFCTRL_PMIE BIT(20)
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#define PMU_ENVENT_ENABLED (CSR_PERFCTRL_PLV0 | CSR_PERFCTRL_PLV1 | CSR_PERFCTRL_PLV2 | CSR_PERFCTRL_PLV3)
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/* Hardware event codes (from LoongArch perf_event.c */
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#define LOONGARCH_PMU_EVENT_CYCLES 0x00 /* CPU cycles */
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#define LOONGARCH_PMU_EVENT_INSTR_RETIRED 0x01 /* Instructions retired */
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#define PERF_COUNT_HW_BRANCH_INSTRUCTIONS 0x02 /* Branch instructions */
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#define PERF_COUNT_HW_BRANCH_MISSES 0x03 /* Branch misses */
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#define NUM_LOOPS 1000
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#define EXPECTED_INSTR_MIN (NUM_LOOPS + 10) /* Loop + overhead */
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#define EXPECTED_CYCLES_MIN NUM_LOOPS /* At least 1 cycle per iteration */
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#define UPPER_BOUND (10 * NUM_LOOPS)
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#define PMU_OVERFLOW (1ULL << 63)
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static inline void pmu_irq_enable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val |= ECFGF_PMU;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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static inline void pmu_irq_disable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val &= ~ECFGF_PMU;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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#endif
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