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1c5bc60f95
Pin the arm64 counterparts of the x86-64 rebase sequences: the single extended-register add for an unconditional argument, the nullable truncate-test-and-skip variant, and all five argument registers in one call. The nullable cases use a local label so the branch is pinned to the instruction right after the add, and the label line does not spell out the call because arm64 emits either a direct bl or a materialize- and-blr pair depending on the distance to the kfunc. Note that on arm64 an unconditional argument is one instruction with nothing to anchor it against, so arena_arg_jit_rebase alone cannot tell the two forms apart; it only requires that nothing is emitted between the rebase and the call. The args5 test is what pins the distinction, since its four consecutive adds leave no room for a nullable truncate-and-branch pair between them. Signed-off-by: Puranjay Mohan <puranjay@kernel.org> Acked-by: Xu Kuohai <xukuohai@huawei.com> Link: https://lore.kernel.org/bpf/20260813190356.335181-6-puranjay@kernel.org Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2026 Meta Platforms, Inc. and affiliates. */
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/*
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* Verify the JIT-emitted rebase sequences for __arena and __arena__nullable
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* kfunc arguments. The capture kfuncs take the argument without
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* dereferencing it, so these tests pin only the emitted code.
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*/
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#define BPF_NO_KFUNC_PROTOTYPES
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#include <vmlinux.h>
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#include <bpf/bpf_helpers.h>
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#include "bpf_misc.h"
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#include "bpf_experimental.h"
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#include <bpf_arena_common.h>
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#include "../test_kmods/bpf_testmod_kfunc.h"
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struct {
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__uint(type, BPF_MAP_TYPE_ARENA);
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__uint(map_flags, BPF_F_MMAPABLE);
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__uint(max_entries, 1);
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} arena SEC(".maps");
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/* volatile to force the scalar reloads below */
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volatile u64 stash;
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#if defined(__BPF_FEATURE_ADDR_SPACE_CAST)
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SEC("syscall")
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__arch_x86_64
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__jited("...")
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__jited(" movl %edi, %edi")
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__jited(" addq %r12, %rdi")
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__jited("...")
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__jited(" callq {{.*}}")
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__arch_arm64
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__jited("...")
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__jited(" add x0, x28, w0, uxtw")
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__jited(" {{(bl|mov) .*}}")
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__success
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int arena_arg_jit_rebase(void *ctx)
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{
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stash = (u64)bpf_arena_alloc_pages(&arena, NULL, 1, NUMA_NO_NODE, 0);
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bpf_kfunc_arena_cap_test((u64 *)stash);
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return 0;
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}
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SEC("syscall")
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__arch_x86_64
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__jited("...")
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__jited(" movl %edi, %edi")
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__jited(" testl %edi, %edi")
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__jited(" je L0")
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__jited(" addq %r12, %rdi")
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__jited("L0: callq {{.*}}")
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__arch_arm64
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__jited("...")
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__jited(" mov w0, w0")
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__jited(" cbz w0, L0")
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__jited(" add x0, x28, w0, uxtw")
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__jited("L0: {{.*}}")
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__success
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int arena_arg_jit_nullable(void *ctx)
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{
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stash = (u64)bpf_arena_alloc_pages(&arena, NULL, 1, NUMA_NO_NODE, 0);
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bpf_kfunc_arena_cap_nullable_test((u64 *)stash);
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return 0;
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}
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SEC("syscall")
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__arch_x86_64
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__jited("...")
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__jited(" movl %edi, %edi")
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__jited(" addq %r12, %rdi")
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__jited(" movl %esi, %esi")
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__jited(" addq %r12, %rsi")
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__jited(" movl %edx, %edx")
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__jited(" addq %r12, %rdx")
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__jited(" movl %ecx, %ecx")
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__jited(" addq %r12, %rcx")
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__jited(" movl %r8d, %r8d")
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__jited(" testl %r8d, %r8d")
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__jited(" je L0")
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__jited(" addq %r12, %r8")
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__jited("L0: callq {{.*}}")
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__arch_arm64
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__jited("...")
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__jited(" add x0, x28, w0, uxtw")
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__jited(" add x1, x28, w1, uxtw")
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__jited(" add x2, x28, w2, uxtw")
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__jited(" add x3, x28, w3, uxtw")
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__jited(" mov w4, w4")
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__jited(" cbz w4, L0")
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__jited(" add x4, x28, w4, uxtw")
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__jited("L0: {{.*}}")
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__success
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int arena_arg_jit_args5(void *ctx)
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{
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u64 __arena *val;
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val = bpf_arena_alloc_pages(&arena, NULL, 1, NUMA_NO_NODE, 0);
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if (!val)
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return 1;
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val[0] = 1;
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val[1] = 2;
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val[2] = 4;
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val[3] = 8;
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val[4] = 16;
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bpf_kfunc_arena_args5_test((u64 *)&val[0], (u64 *)&val[1],
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(u64 *)&val[2], (u64 *)&val[3],
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(u64 *)&val[4]);
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return 0;
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}
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#endif /* __BPF_FEATURE_ADDR_SPACE_CAST */
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char _license[] SEC("license") = "GPL";
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