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033bee3e49
Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Link: https://lkml.kernel.org/r/20260327061704.3707577-15-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Eric Biggers <ebiggers@kernel.org> Tested-by: Eric Biggers <ebiggers@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Andreas Larsson <andreas@gaisler.com> Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David S. Miller <davem@davemloft.net> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jason A. Donenfeld <jason@zx2c4.com> Cc: Johannes Berg <johannes@sipsolutions.net> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Magnus Lindholm <linmag7@gmail.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@armlinux.org.uk> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Ted Ts'o <tytso@mit.edu> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* LoongArch SIMD XOR operations
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*
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* Copyright (C) 2023 WANG Xuerui <git@xen0n.name>
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*/
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#include "xor_simd.h"
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/*
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* Process one cache line (64 bytes) per loop. This is assuming all future
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* popular LoongArch cores are similar performance-characteristics-wise to the
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* current models.
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*/
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#define LINE_WIDTH 64
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#ifdef CONFIG_CPU_HAS_LSX
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#define LD(reg, base, offset) \
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"vld $vr" #reg ", %[" #base "], " #offset "\n\t"
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#define ST(reg, base, offset) \
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"vst $vr" #reg ", %[" #base "], " #offset "\n\t"
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#define XOR(dj, k) "vxor.v $vr" #dj ", $vr" #dj ", $vr" #k "\n\t"
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#define LD_INOUT_LINE(base) \
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LD(0, base, 0) \
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LD(1, base, 16) \
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LD(2, base, 32) \
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LD(3, base, 48)
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#define LD_AND_XOR_LINE(base) \
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LD(4, base, 0) \
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LD(5, base, 16) \
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LD(6, base, 32) \
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LD(7, base, 48) \
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XOR(0, 4) \
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XOR(1, 5) \
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XOR(2, 6) \
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XOR(3, 7)
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#define ST_LINE(base) \
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ST(0, base, 0) \
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ST(1, base, 16) \
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ST(2, base, 32) \
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ST(3, base, 48)
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#define XOR_FUNC_NAME(nr) __xor_lsx_##nr
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#include "xor_template.c"
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#undef LD
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#undef ST
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#undef XOR
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#undef LD_INOUT_LINE
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#undef LD_AND_XOR_LINE
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#undef ST_LINE
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#undef XOR_FUNC_NAME
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#endif /* CONFIG_CPU_HAS_LSX */
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#ifdef CONFIG_CPU_HAS_LASX
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#define LD(reg, base, offset) \
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"xvld $xr" #reg ", %[" #base "], " #offset "\n\t"
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#define ST(reg, base, offset) \
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"xvst $xr" #reg ", %[" #base "], " #offset "\n\t"
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#define XOR(dj, k) "xvxor.v $xr" #dj ", $xr" #dj ", $xr" #k "\n\t"
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#define LD_INOUT_LINE(base) \
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LD(0, base, 0) \
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LD(1, base, 32)
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#define LD_AND_XOR_LINE(base) \
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LD(2, base, 0) \
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LD(3, base, 32) \
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XOR(0, 2) \
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XOR(1, 3)
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#define ST_LINE(base) \
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ST(0, base, 0) \
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ST(1, base, 32)
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#define XOR_FUNC_NAME(nr) __xor_lasx_##nr
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#include "xor_template.c"
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#undef LD
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#undef ST
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#undef XOR
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#undef LD_INOUT_LINE
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#undef LD_AND_XOR_LINE
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#undef ST_LINE
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#undef XOR_FUNC_NAME
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#endif /* CONFIG_CPU_HAS_LASX */
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