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Replace the static array of algorithms with a call to an architecture helper to register algorithms. This serves two purposes: it avoid having to register all algorithms in a single central place, and it removes the need for the priority field by just registering the algorithms that the architecture considers suitable for the currently running CPUs. [hch@lst.de: register avx512 after avx2] Link: https://lore.kernel.org/20260527074539.2292913-3-hch@lst.de Link: https://lore.kernel.org/20260518051804.462141-11-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> # kunit only on arm64 Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
83 lines
2.3 KiB
Ucode
83 lines
2.3 KiB
Ucode
/*
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* Copyright 2017, Matt Brown, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* vpermxor$#.c
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*
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* Based on H. Peter Anvin's paper - The mathematics of RAID-6
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*
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* $#-way unrolled portable integer math RAID-6 instruction set
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* This file is postprocessed using unroll.awk
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*
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* vpermxor$#.c makes use of the vpermxor instruction to optimise the RAID6 Q
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* syndrome calculations.
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* This can be run on systems which have both Altivec and vpermxor instruction.
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*
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* This instruction was introduced in POWER8 - ISA v2.07.
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*/
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#include <altivec.h>
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#include <asm/ppc-opcode.h>
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#include <asm/cputable.h>
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#include <asm/switch_to.h>
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#include "algos.h"
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typedef vector unsigned char unative_t;
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#define NSIZE sizeof(unative_t)
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static const vector unsigned char gf_low = {0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14,
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0x12, 0x10, 0x0e, 0x0c, 0x0a, 0x08,
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0x06, 0x04, 0x02,0x00};
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static const vector unsigned char gf_high = {0xfd, 0xdd, 0xbd, 0x9d, 0x7d, 0x5d,
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0x3d, 0x1d, 0xe0, 0xc0, 0xa0, 0x80,
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0x60, 0x40, 0x20, 0x00};
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static void noinline raid6_vpermxor$#_gen_syndrome_real(int disks, size_t bytes,
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void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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unative_t wp$$, wq$$, wd$$;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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for (d = 0; d < bytes; d += NSIZE*$#) {
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wp$$ = wq$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
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for (z = z0-1; z>=0; z--) {
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wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
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/* P syndrome */
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wp$$ = vec_xor(wp$$, wd$$);
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/* Q syndrome */
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asm(VPERMXOR(%0,%1,%2,%3):"=v"(wq$$):"v"(gf_high), "v"(gf_low), "v"(wq$$));
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wq$$ = vec_xor(wq$$, wd$$);
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}
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*(unative_t *)&p[d+NSIZE*$$] = wp$$;
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*(unative_t *)&q[d+NSIZE*$$] = wq$$;
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}
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}
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static void raid6_vpermxor$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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preempt_disable();
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enable_kernel_altivec();
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raid6_vpermxor$#_gen_syndrome_real(disks, bytes, ptrs);
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disable_kernel_altivec();
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preempt_enable();
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}
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const struct raid6_calls raid6_vpermxor$# = {
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.gen_syndrome = raid6_vpermxor$#_gen_syndrome,
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.name = "vpermxor$#",
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};
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