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adfcf6e89b
Replace the static array of algorithms with a call to an architecture helper to register algorithms. This serves two purposes: it avoid having to register all algorithms in a single central place, and it removes the need for the priority field by just registering the algorithms that the architecture considers suitable for the currently running CPUs. [hch@lst.de: register avx512 after avx2] Link: https://lore.kernel.org/20260527074539.2292913-3-hch@lst.de Link: https://lore.kernel.org/20260518051804.462141-11-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> # kunit only on arm64 Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
111 lines
3.0 KiB
Ucode
111 lines
3.0 KiB
Ucode
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* raid6altivec$#.c
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*
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* $#-way unrolled portable integer math RAID-6 instruction set
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*
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* This file is postprocessed using unroll.awk
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*
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* <benh> hpa: in process,
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* you can just "steal" the vec unit with enable_kernel_altivec() (but
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* bracked this with preempt_disable/enable or in a lock)
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*/
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#include "algos.h"
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#include <altivec.h>
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#include <asm/cputable.h>
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#include <asm/switch_to.h>
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/*
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* This is the C data type to use. We use a vector of
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* signed char so vec_cmpgt() will generate the right
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* instruction.
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*/
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typedef vector signed char unative_t;
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#define NBYTES(x) ((vector signed char) {x,x,x,x, x,x,x,x, x,x,x,x, x,x,x,x})
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#define NSIZE sizeof(unative_t)
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/*
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* The SHLBYTE() operation shifts each byte left by 1, *not*
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* rolling over into the next byte
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*/
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static inline __attribute_const__ unative_t SHLBYTE(unative_t v)
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{
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return vec_add(v,v);
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}
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/*
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* The MASK() operation returns 0xFF in any byte for which the high
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* bit is 1, 0x00 for any byte for which the high bit is 0.
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*/
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static inline __attribute_const__ unative_t MASK(unative_t v)
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{
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unative_t zv = NBYTES(0);
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/* vec_cmpgt returns a vector bool char; thus the need for the cast */
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return (unative_t)vec_cmpgt(zv, v);
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}
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/* This is noinline to make damned sure that gcc doesn't move any of the
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Altivec code around the enable/disable code */
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static void noinline
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raid6_altivec$#_gen_syndrome_real(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
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unative_t x1d = NBYTES(0x1d);
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
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wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
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for ( z = z0-1 ; z >= 0 ; z-- ) {
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wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
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wp$$ = vec_xor(wp$$, wd$$);
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w2$$ = MASK(wq$$);
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w1$$ = SHLBYTE(wq$$);
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w2$$ = vec_and(w2$$, x1d);
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w1$$ = vec_xor(w1$$, w2$$);
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wq$$ = vec_xor(w1$$, wd$$);
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}
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*(unative_t *)&p[d+NSIZE*$$] = wp$$;
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*(unative_t *)&q[d+NSIZE*$$] = wq$$;
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}
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}
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static void raid6_altivec$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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preempt_disable();
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enable_kernel_altivec();
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raid6_altivec$#_gen_syndrome_real(disks, bytes, ptrs);
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disable_kernel_altivec();
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preempt_enable();
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}
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const struct raid6_calls raid6_altivec$# = {
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.gen_syndrome = raid6_altivec$#_gen_syndrome,
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.name = "altivecx$#",
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};
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