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adfcf6e89b
Replace the static array of algorithms with a call to an architecture helper to register algorithms. This serves two purposes: it avoid having to register all algorithms in a single central place, and it removes the need for the priority field by just registering the algorithms that the architecture considers suitable for the currently running CPUs. [hch@lst.de: register avx512 after avx2] Link: https://lore.kernel.org/20260527074539.2292913-3-hch@lst.de Link: https://lore.kernel.org/20260518051804.462141-11-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> # kunit only on arm64 Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
410 lines
13 KiB
C
410 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* RAID6 syndrome calculations in LoongArch SIMD (LSX & LASX)
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*
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* Copyright 2023 WANG Xuerui <git@xen0n.name>
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*
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* Based on the generic RAID-6 code (int.uc):
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*
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* Copyright 2002-2004 H. Peter Anvin
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*/
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#include <asm/cpu-features.h>
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#include <asm/fpu.h>
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#include "algos.h"
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/*
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* The vector algorithms are currently priority 0, which means the generic
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* scalar algorithms are not being disabled if vector support is present.
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* This is like the similar LoongArch RAID5 XOR code, with the main reason
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* repeated here: it cannot be ruled out at this point of time, that some
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* future (maybe reduced) models could run the vector algorithms slower than
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* the scalar ones, maybe for errata or micro-op reasons. It may be
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* appropriate to revisit this after one or two more uarch generations.
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*/
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#ifdef CONFIG_CPU_HAS_LSX
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#define NSIZE 16
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static void raid6_lsx_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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/*
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* $vr0, $vr1, $vr2, $vr3: wp
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* $vr4, $vr5, $vr6, $vr7: wq
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* $vr8, $vr9, $vr10, $vr11: wd
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* $vr12, $vr13, $vr14, $vr15: w2
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* $vr16, $vr17, $vr18, $vr19: w1
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*/
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for (d = 0; d < bytes; d += NSIZE*4) {
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/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
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asm volatile("vld $vr0, %0" : : "m"(dptr[z0][d+0*NSIZE]));
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asm volatile("vld $vr1, %0" : : "m"(dptr[z0][d+1*NSIZE]));
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asm volatile("vld $vr2, %0" : : "m"(dptr[z0][d+2*NSIZE]));
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asm volatile("vld $vr3, %0" : : "m"(dptr[z0][d+3*NSIZE]));
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asm volatile("vori.b $vr4, $vr0, 0");
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asm volatile("vori.b $vr5, $vr1, 0");
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asm volatile("vori.b $vr6, $vr2, 0");
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asm volatile("vori.b $vr7, $vr3, 0");
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for (z = z0-1; z >= 0; z--) {
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/* wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; */
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asm volatile("vld $vr8, %0" : : "m"(dptr[z][d+0*NSIZE]));
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asm volatile("vld $vr9, %0" : : "m"(dptr[z][d+1*NSIZE]));
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asm volatile("vld $vr10, %0" : : "m"(dptr[z][d+2*NSIZE]));
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asm volatile("vld $vr11, %0" : : "m"(dptr[z][d+3*NSIZE]));
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/* wp$$ ^= wd$$; */
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asm volatile("vxor.v $vr0, $vr0, $vr8");
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asm volatile("vxor.v $vr1, $vr1, $vr9");
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asm volatile("vxor.v $vr2, $vr2, $vr10");
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asm volatile("vxor.v $vr3, $vr3, $vr11");
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/* w2$$ = MASK(wq$$); */
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asm volatile("vslti.b $vr12, $vr4, 0");
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asm volatile("vslti.b $vr13, $vr5, 0");
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asm volatile("vslti.b $vr14, $vr6, 0");
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asm volatile("vslti.b $vr15, $vr7, 0");
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/* w1$$ = SHLBYTE(wq$$); */
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asm volatile("vslli.b $vr16, $vr4, 1");
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asm volatile("vslli.b $vr17, $vr5, 1");
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asm volatile("vslli.b $vr18, $vr6, 1");
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asm volatile("vslli.b $vr19, $vr7, 1");
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/* w2$$ &= NBYTES(0x1d); */
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asm volatile("vandi.b $vr12, $vr12, 0x1d");
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asm volatile("vandi.b $vr13, $vr13, 0x1d");
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asm volatile("vandi.b $vr14, $vr14, 0x1d");
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asm volatile("vandi.b $vr15, $vr15, 0x1d");
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/* w1$$ ^= w2$$; */
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asm volatile("vxor.v $vr16, $vr16, $vr12");
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asm volatile("vxor.v $vr17, $vr17, $vr13");
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asm volatile("vxor.v $vr18, $vr18, $vr14");
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asm volatile("vxor.v $vr19, $vr19, $vr15");
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/* wq$$ = w1$$ ^ wd$$; */
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asm volatile("vxor.v $vr4, $vr16, $vr8");
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asm volatile("vxor.v $vr5, $vr17, $vr9");
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asm volatile("vxor.v $vr6, $vr18, $vr10");
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asm volatile("vxor.v $vr7, $vr19, $vr11");
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}
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/* *(unative_t *)&p[d+NSIZE*$$] = wp$$; */
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asm volatile("vst $vr0, %0" : "=m"(p[d+NSIZE*0]));
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asm volatile("vst $vr1, %0" : "=m"(p[d+NSIZE*1]));
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asm volatile("vst $vr2, %0" : "=m"(p[d+NSIZE*2]));
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asm volatile("vst $vr3, %0" : "=m"(p[d+NSIZE*3]));
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/* *(unative_t *)&q[d+NSIZE*$$] = wq$$; */
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asm volatile("vst $vr4, %0" : "=m"(q[d+NSIZE*0]));
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asm volatile("vst $vr5, %0" : "=m"(q[d+NSIZE*1]));
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asm volatile("vst $vr6, %0" : "=m"(q[d+NSIZE*2]));
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asm volatile("vst $vr7, %0" : "=m"(q[d+NSIZE*3]));
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}
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kernel_fpu_end();
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}
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static void raid6_lsx_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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/*
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* $vr0, $vr1, $vr2, $vr3: wp
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* $vr4, $vr5, $vr6, $vr7: wq
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* $vr8, $vr9, $vr10, $vr11: wd
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* $vr12, $vr13, $vr14, $vr15: w2
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* $vr16, $vr17, $vr18, $vr19: w1
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*/
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for (d = 0; d < bytes; d += NSIZE*4) {
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/* P/Q data pages */
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/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
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asm volatile("vld $vr0, %0" : : "m"(dptr[z0][d+0*NSIZE]));
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asm volatile("vld $vr1, %0" : : "m"(dptr[z0][d+1*NSIZE]));
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asm volatile("vld $vr2, %0" : : "m"(dptr[z0][d+2*NSIZE]));
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asm volatile("vld $vr3, %0" : : "m"(dptr[z0][d+3*NSIZE]));
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asm volatile("vori.b $vr4, $vr0, 0");
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asm volatile("vori.b $vr5, $vr1, 0");
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asm volatile("vori.b $vr6, $vr2, 0");
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asm volatile("vori.b $vr7, $vr3, 0");
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for (z = z0-1; z >= start; z--) {
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/* wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; */
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asm volatile("vld $vr8, %0" : : "m"(dptr[z][d+0*NSIZE]));
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asm volatile("vld $vr9, %0" : : "m"(dptr[z][d+1*NSIZE]));
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asm volatile("vld $vr10, %0" : : "m"(dptr[z][d+2*NSIZE]));
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asm volatile("vld $vr11, %0" : : "m"(dptr[z][d+3*NSIZE]));
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/* wp$$ ^= wd$$; */
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asm volatile("vxor.v $vr0, $vr0, $vr8");
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asm volatile("vxor.v $vr1, $vr1, $vr9");
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asm volatile("vxor.v $vr2, $vr2, $vr10");
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asm volatile("vxor.v $vr3, $vr3, $vr11");
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/* w2$$ = MASK(wq$$); */
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asm volatile("vslti.b $vr12, $vr4, 0");
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asm volatile("vslti.b $vr13, $vr5, 0");
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asm volatile("vslti.b $vr14, $vr6, 0");
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asm volatile("vslti.b $vr15, $vr7, 0");
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/* w1$$ = SHLBYTE(wq$$); */
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asm volatile("vslli.b $vr16, $vr4, 1");
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asm volatile("vslli.b $vr17, $vr5, 1");
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asm volatile("vslli.b $vr18, $vr6, 1");
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asm volatile("vslli.b $vr19, $vr7, 1");
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/* w2$$ &= NBYTES(0x1d); */
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asm volatile("vandi.b $vr12, $vr12, 0x1d");
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asm volatile("vandi.b $vr13, $vr13, 0x1d");
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asm volatile("vandi.b $vr14, $vr14, 0x1d");
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asm volatile("vandi.b $vr15, $vr15, 0x1d");
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/* w1$$ ^= w2$$; */
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asm volatile("vxor.v $vr16, $vr16, $vr12");
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asm volatile("vxor.v $vr17, $vr17, $vr13");
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asm volatile("vxor.v $vr18, $vr18, $vr14");
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asm volatile("vxor.v $vr19, $vr19, $vr15");
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/* wq$$ = w1$$ ^ wd$$; */
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asm volatile("vxor.v $vr4, $vr16, $vr8");
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asm volatile("vxor.v $vr5, $vr17, $vr9");
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asm volatile("vxor.v $vr6, $vr18, $vr10");
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asm volatile("vxor.v $vr7, $vr19, $vr11");
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}
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/* P/Q left side optimization */
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for (z = start-1; z >= 0; z--) {
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/* w2$$ = MASK(wq$$); */
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asm volatile("vslti.b $vr12, $vr4, 0");
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asm volatile("vslti.b $vr13, $vr5, 0");
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asm volatile("vslti.b $vr14, $vr6, 0");
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asm volatile("vslti.b $vr15, $vr7, 0");
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/* w1$$ = SHLBYTE(wq$$); */
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asm volatile("vslli.b $vr16, $vr4, 1");
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asm volatile("vslli.b $vr17, $vr5, 1");
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asm volatile("vslli.b $vr18, $vr6, 1");
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asm volatile("vslli.b $vr19, $vr7, 1");
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/* w2$$ &= NBYTES(0x1d); */
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asm volatile("vandi.b $vr12, $vr12, 0x1d");
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asm volatile("vandi.b $vr13, $vr13, 0x1d");
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asm volatile("vandi.b $vr14, $vr14, 0x1d");
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asm volatile("vandi.b $vr15, $vr15, 0x1d");
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/* wq$$ = w1$$ ^ w2$$; */
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asm volatile("vxor.v $vr4, $vr16, $vr12");
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asm volatile("vxor.v $vr5, $vr17, $vr13");
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asm volatile("vxor.v $vr6, $vr18, $vr14");
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asm volatile("vxor.v $vr7, $vr19, $vr15");
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}
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/*
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* *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
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* *(unative_t *)&q[d+NSIZE*$$] ^= wq$$;
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*/
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asm volatile(
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"vld $vr20, %0\n\t"
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"vld $vr21, %1\n\t"
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"vld $vr22, %2\n\t"
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"vld $vr23, %3\n\t"
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"vld $vr24, %4\n\t"
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"vld $vr25, %5\n\t"
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"vld $vr26, %6\n\t"
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"vld $vr27, %7\n\t"
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"vxor.v $vr20, $vr20, $vr0\n\t"
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"vxor.v $vr21, $vr21, $vr1\n\t"
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"vxor.v $vr22, $vr22, $vr2\n\t"
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"vxor.v $vr23, $vr23, $vr3\n\t"
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"vxor.v $vr24, $vr24, $vr4\n\t"
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"vxor.v $vr25, $vr25, $vr5\n\t"
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"vxor.v $vr26, $vr26, $vr6\n\t"
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"vxor.v $vr27, $vr27, $vr7\n\t"
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"vst $vr20, %0\n\t"
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"vst $vr21, %1\n\t"
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"vst $vr22, %2\n\t"
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"vst $vr23, %3\n\t"
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"vst $vr24, %4\n\t"
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"vst $vr25, %5\n\t"
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"vst $vr26, %6\n\t"
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"vst $vr27, %7\n\t"
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: "+m"(p[d+NSIZE*0]), "+m"(p[d+NSIZE*1]),
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"+m"(p[d+NSIZE*2]), "+m"(p[d+NSIZE*3]),
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"+m"(q[d+NSIZE*0]), "+m"(q[d+NSIZE*1]),
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"+m"(q[d+NSIZE*2]), "+m"(q[d+NSIZE*3])
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);
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}
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_lsx = {
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.gen_syndrome = raid6_lsx_gen_syndrome,
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.xor_syndrome = raid6_lsx_xor_syndrome,
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.name = "lsx",
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};
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#undef NSIZE
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#endif /* CONFIG_CPU_HAS_LSX */
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#ifdef CONFIG_CPU_HAS_LASX
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#define NSIZE 32
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static void raid6_lasx_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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/*
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* $xr0, $xr1: wp
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* $xr2, $xr3: wq
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* $xr4, $xr5: wd
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* $xr6, $xr7: w2
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* $xr8, $xr9: w1
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*/
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for (d = 0; d < bytes; d += NSIZE*2) {
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/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
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asm volatile("xvld $xr0, %0" : : "m"(dptr[z0][d+0*NSIZE]));
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asm volatile("xvld $xr1, %0" : : "m"(dptr[z0][d+1*NSIZE]));
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asm volatile("xvori.b $xr2, $xr0, 0");
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asm volatile("xvori.b $xr3, $xr1, 0");
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for (z = z0-1; z >= 0; z--) {
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/* wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; */
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asm volatile("xvld $xr4, %0" : : "m"(dptr[z][d+0*NSIZE]));
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asm volatile("xvld $xr5, %0" : : "m"(dptr[z][d+1*NSIZE]));
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/* wp$$ ^= wd$$; */
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asm volatile("xvxor.v $xr0, $xr0, $xr4");
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asm volatile("xvxor.v $xr1, $xr1, $xr5");
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/* w2$$ = MASK(wq$$); */
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asm volatile("xvslti.b $xr6, $xr2, 0");
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asm volatile("xvslti.b $xr7, $xr3, 0");
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/* w1$$ = SHLBYTE(wq$$); */
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asm volatile("xvslli.b $xr8, $xr2, 1");
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asm volatile("xvslli.b $xr9, $xr3, 1");
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/* w2$$ &= NBYTES(0x1d); */
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asm volatile("xvandi.b $xr6, $xr6, 0x1d");
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asm volatile("xvandi.b $xr7, $xr7, 0x1d");
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/* w1$$ ^= w2$$; */
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asm volatile("xvxor.v $xr8, $xr8, $xr6");
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asm volatile("xvxor.v $xr9, $xr9, $xr7");
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/* wq$$ = w1$$ ^ wd$$; */
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asm volatile("xvxor.v $xr2, $xr8, $xr4");
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asm volatile("xvxor.v $xr3, $xr9, $xr5");
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}
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/* *(unative_t *)&p[d+NSIZE*$$] = wp$$; */
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asm volatile("xvst $xr0, %0" : "=m"(p[d+NSIZE*0]));
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asm volatile("xvst $xr1, %0" : "=m"(p[d+NSIZE*1]));
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/* *(unative_t *)&q[d+NSIZE*$$] = wq$$; */
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asm volatile("xvst $xr2, %0" : "=m"(q[d+NSIZE*0]));
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asm volatile("xvst $xr3, %0" : "=m"(q[d+NSIZE*1]));
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}
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kernel_fpu_end();
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}
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static void raid6_lasx_xor_syndrome(int disks, int start, int stop,
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size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = stop; /* P/Q right side optimization */
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p = dptr[disks-2]; /* XOR parity */
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q = dptr[disks-1]; /* RS syndrome */
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kernel_fpu_begin();
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/*
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* $xr0, $xr1: wp
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* $xr2, $xr3: wq
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* $xr4, $xr5: wd
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* $xr6, $xr7: w2
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|
* $xr8, $xr9: w1
|
|
*/
|
|
for (d = 0; d < bytes; d += NSIZE*2) {
|
|
/* P/Q data pages */
|
|
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
|
|
asm volatile("xvld $xr0, %0" : : "m"(dptr[z0][d+0*NSIZE]));
|
|
asm volatile("xvld $xr1, %0" : : "m"(dptr[z0][d+1*NSIZE]));
|
|
asm volatile("xvori.b $xr2, $xr0, 0");
|
|
asm volatile("xvori.b $xr3, $xr1, 0");
|
|
for (z = z0-1; z >= start; z--) {
|
|
/* wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE]; */
|
|
asm volatile("xvld $xr4, %0" : : "m"(dptr[z][d+0*NSIZE]));
|
|
asm volatile("xvld $xr5, %0" : : "m"(dptr[z][d+1*NSIZE]));
|
|
/* wp$$ ^= wd$$; */
|
|
asm volatile("xvxor.v $xr0, $xr0, $xr4");
|
|
asm volatile("xvxor.v $xr1, $xr1, $xr5");
|
|
/* w2$$ = MASK(wq$$); */
|
|
asm volatile("xvslti.b $xr6, $xr2, 0");
|
|
asm volatile("xvslti.b $xr7, $xr3, 0");
|
|
/* w1$$ = SHLBYTE(wq$$); */
|
|
asm volatile("xvslli.b $xr8, $xr2, 1");
|
|
asm volatile("xvslli.b $xr9, $xr3, 1");
|
|
/* w2$$ &= NBYTES(0x1d); */
|
|
asm volatile("xvandi.b $xr6, $xr6, 0x1d");
|
|
asm volatile("xvandi.b $xr7, $xr7, 0x1d");
|
|
/* w1$$ ^= w2$$; */
|
|
asm volatile("xvxor.v $xr8, $xr8, $xr6");
|
|
asm volatile("xvxor.v $xr9, $xr9, $xr7");
|
|
/* wq$$ = w1$$ ^ wd$$; */
|
|
asm volatile("xvxor.v $xr2, $xr8, $xr4");
|
|
asm volatile("xvxor.v $xr3, $xr9, $xr5");
|
|
}
|
|
|
|
/* P/Q left side optimization */
|
|
for (z = start-1; z >= 0; z--) {
|
|
/* w2$$ = MASK(wq$$); */
|
|
asm volatile("xvslti.b $xr6, $xr2, 0");
|
|
asm volatile("xvslti.b $xr7, $xr3, 0");
|
|
/* w1$$ = SHLBYTE(wq$$); */
|
|
asm volatile("xvslli.b $xr8, $xr2, 1");
|
|
asm volatile("xvslli.b $xr9, $xr3, 1");
|
|
/* w2$$ &= NBYTES(0x1d); */
|
|
asm volatile("xvandi.b $xr6, $xr6, 0x1d");
|
|
asm volatile("xvandi.b $xr7, $xr7, 0x1d");
|
|
/* wq$$ = w1$$ ^ w2$$; */
|
|
asm volatile("xvxor.v $xr2, $xr8, $xr6");
|
|
asm volatile("xvxor.v $xr3, $xr9, $xr7");
|
|
}
|
|
/*
|
|
* *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
|
|
* *(unative_t *)&q[d+NSIZE*$$] ^= wq$$;
|
|
*/
|
|
asm volatile(
|
|
"xvld $xr10, %0\n\t"
|
|
"xvld $xr11, %1\n\t"
|
|
"xvld $xr12, %2\n\t"
|
|
"xvld $xr13, %3\n\t"
|
|
"xvxor.v $xr10, $xr10, $xr0\n\t"
|
|
"xvxor.v $xr11, $xr11, $xr1\n\t"
|
|
"xvxor.v $xr12, $xr12, $xr2\n\t"
|
|
"xvxor.v $xr13, $xr13, $xr3\n\t"
|
|
"xvst $xr10, %0\n\t"
|
|
"xvst $xr11, %1\n\t"
|
|
"xvst $xr12, %2\n\t"
|
|
"xvst $xr13, %3\n\t"
|
|
: "+m"(p[d+NSIZE*0]), "+m"(p[d+NSIZE*1]),
|
|
"+m"(q[d+NSIZE*0]), "+m"(q[d+NSIZE*1])
|
|
);
|
|
}
|
|
|
|
kernel_fpu_end();
|
|
}
|
|
|
|
const struct raid6_calls raid6_lasx = {
|
|
.gen_syndrome = raid6_lasx_gen_syndrome,
|
|
.xor_syndrome = raid6_lasx_xor_syndrome,
|
|
.name = "lasx",
|
|
};
|
|
#undef NSIZE
|
|
#endif /* CONFIG_CPU_HAS_LASX */
|