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b06cf63d83
According to the UFS spec, the bRefClkFreq attribute can only be written when both sub-links are in LS-MODE. However, in HS LSS mode with resetmode = HS_MODE, if the UFS device's default bRefClkFreq value differs from the host controller's dev_ref_clk_freq setting, the write operation will fail. To fix this issue, introduce ufshcd_get_op_mode() function to detect the current link operational mode. Call ufshcd_set_dev_ref_clk() only when both sub-links are in LS-MODE to ensure the attribute can be written successfully. Signed-off-by: Wang Shuaiwei <wangshuaiwei1@xiaomi.com> Link: https://patch.msgid.link/20260414033718.1459540-1-wangshuaiwei1@xiaomi.com Reviewed-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
470 lines
14 KiB
C
470 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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*/
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#ifndef _UNIPRO_H_
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#define _UNIPRO_H_
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/*
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* M-TX Configuration Attributes
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*/
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#define TX_HIBERN8TIME_CAPABILITY 0x000F
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#define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012
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#define TX_HS_PRESHOOT_SETTING_CAP 0x0015
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#define TX_MODE 0x0021
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#define TX_HSRATE_SERIES 0x0022
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#define TX_HSGEAR 0x0023
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#define TX_PWMGEAR 0x0024
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#define TX_AMPLITUDE 0x0025
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#define TX_HS_SLEWRATE 0x0026
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#define TX_SYNC_SOURCE 0x0027
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#define TX_HS_SYNC_LENGTH 0x0028
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#define TX_HS_PREPARE_LENGTH 0x0029
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#define TX_LS_PREPARE_LENGTH 0x002A
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#define TX_HIBERN8_CONTROL 0x002B
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#define TX_LCC_ENABLE 0x002C
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#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
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#define TX_BYPASS_8B10B_ENABLE 0x002E
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#define TX_DRIVER_POLARITY 0x002F
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#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
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#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
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#define TX_LCC_SEQUENCER 0x0032
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#define TX_MIN_ACTIVATETIME 0x0033
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#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
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#define TX_HS_DEEMPHASIS_SETTING 0x0037
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#define TX_HS_PRESHOOT_SETTING 0x003B
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#define TX_REFCLKFREQ 0x00EB
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#define TX_CFGCLKFREQVAL 0x00EC
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#define CFGEXTRATTR 0x00F0
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#define DITHERCTRL2 0x00F1
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/*
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* M-RX Configuration Attributes
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*/
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#define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074
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#define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B
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#define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D
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#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
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#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
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#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
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#define RX_HIBERN8TIME_CAPABILITY 0x0092
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#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
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#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
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#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
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#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
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#define RX_ADV_GRANULARITY_CAP 0x0098
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#define RX_HIBERN8TIME_CAP 0x0092
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#define RX_ADV_HIBERN8TIME_CAP 0x0099
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#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
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#define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F
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#define RX_MODE 0x00A1
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#define RX_HSRATE_SERIES 0x00A2
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#define RX_HSGEAR 0x00A3
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#define RX_PWMGEAR 0x00A4
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#define RX_LS_TERMINATED_ENABLE 0x00A5
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#define RX_HS_UNTERMINATED_ENABLE 0x00A6
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#define RX_ENTER_HIBERN8 0x00A7
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#define RX_BYPASS_8B10B_ENABLE 0x00A8
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#define RX_TERMINATION_FORCE_ENABLE 0x00A9
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#define RXCALCTRL 0x00B4
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#define RXSQCTRL 0x00B5
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#define CFGRXCDR8 0x00BA
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#define CFGRXOVR8 0x00BD
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#define CFGRXOVR6 0x00BF
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#define RX_FOM 0x00C2
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#define RXDIRECTCTRL2 0x00C7
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#define CFGRXOVR4 0x00E9
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#define RX_REFCLKFREQ 0x00EB
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#define RX_CFGCLKFREQVAL 0x00EC
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#define CFGWIDEINLN 0x00F0
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#define RX_EYEMON_CAP 0x00F1
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#define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2
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#define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3
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#define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4
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#define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5
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#define RX_EYEMON_ENABLE 0x00F6
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#define RX_EYEMON_TIMING_STEPS 0x00F7
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#define RX_EYEMON_VOLTAGE_STEPS 0x00F8
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#define RX_EYEMON_TARGET_TEST_COUNT 0x00F9
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#define RX_EYEMON_TESTED_COUNT 0x00FA
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#define RX_EYEMON_ERROR_COUNT 0x00FB
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#define RX_EYEMON_START 0x00FC
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#define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD
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#define ENARXDIRECTCFG4 0x00F2
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#define ENARXDIRECTCFG3 0x00F3
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#define ENARXDIRECTCFG2 0x00F4
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#define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6)
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#define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6)
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#define is_mphy_tx_attr(attr) (attr < RX_MODE)
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#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
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#define SYNC_LEN_FINE(x) ((x) & 0x3F)
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#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
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#define PREP_LEN(x) ((x) & 0xF)
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#define RX_MIN_ACTIVATETIME_UNIT_US 100
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#define HIBERN8TIME_UNIT_US 100
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/*
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* Common Block Attributes
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*/
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#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
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#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
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#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
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#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
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#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
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#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
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#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
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#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
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#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
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#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
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#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
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#define ADAPT_LENGTH_MASK 0x7F
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#define ADAPT_RANGE_BIT BIT(7)
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#define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT)
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/* Adapt definitions */
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#define ADAPT_LENGTH_MAX 0x91
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#define ADAPT_L0L3_LENGTH_MAX 0x90
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#define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C
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#define TADAPT_FACTOR 650
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#define TADAPT_L0L3_FACTOR (1 << 9)
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#define TADAPT_L0L1L2L3_FACTOR (1 << 15)
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/*
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* PHY Adapter attributes
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*/
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#define PA_PHY_TYPE 0x1500
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#define PA_AVAILTXDATALANES 0x1520
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#define PA_MAXTXSPEEDFAST 0x1521
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#define PA_MAXTXSPEEDSLOW 0x1522
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#define PA_MAXRXSPEEDFAST 0x1541
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#define PA_MAXRXSPEEDSLOW 0x1542
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#define PA_TXLINKSTARTUPHS 0x1544
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#define PA_AVAILRXDATALANES 0x1540
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#define PA_MINRXTRAILINGCLOCKS 0x1543
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#define PA_TXHSG1SYNCLENGTH 0x1552
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#define PA_TXHSG2SYNCLENGTH 0x1554
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#define PA_TXHSG3SYNCLENGTH 0x1556
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#define PA_LOCAL_TX_LCC_ENABLE 0x155E
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#define PA_ACTIVETXDATALANES 0x1560
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#define PA_CONNECTEDTXDATALANES 0x1561
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#define PA_TXFORCECLOCK 0x1562
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#define PA_TXPWRMODE 0x1563
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#define PA_TXTRAILINGCLOCKS 0x1564
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#define PA_TXSPEEDFAST 0x1565
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#define PA_TXSPEEDSLOW 0x1566
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#define PA_TXPWRSTATUS 0x1567
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#define PA_TXGEAR 0x1568
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#define PA_TXTERMINATION 0x1569
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#define PA_HSSERIES 0x156A
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#define PA_LEGACYDPHYESCDL 0x1570
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#define PA_PWRMODE 0x1571
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#define PA_ACTIVERXDATALANES 0x1580
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#define PA_CONNECTEDRXDATALANES 0x1581
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#define PA_RXPWRSTATUS 0x1582
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#define PA_RXGEAR 0x1583
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#define PA_RXTERMINATION 0x1584
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#define PA_MAXRXPWMGEAR 0x1586
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#define PA_MAXRXHSGEAR 0x1587
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#define PA_PACPREQTIMEOUT 0x1590
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#define PA_PACPREQEOBTIMEOUT 0x1591
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#define PA_REMOTEVERINFO 0x15A0
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#define PA_LOGICALLANEMAP 0x15A1
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#define PA_SLEEPNOCONFIGTIME 0x15A2
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#define PA_STALLNOCONFIGTIME 0x15A3
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#define PA_SAVECONFIGTIME 0x15A4
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#define PA_RXHSUNTERMCAP 0x15A5
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#define PA_RXLSTERMCAP 0x15A6
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#define PA_HIBERN8TIME 0x15A7
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#define PA_LOCALVERINFO 0x15A9
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#define PA_GRANULARITY 0x15AA
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#define PA_TACTIVATE 0x15A8
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#define PA_PWRMODEUSERDATA0 0x15B0
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#define PA_PWRMODEUSERDATA1 0x15B1
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#define PA_PWRMODEUSERDATA2 0x15B2
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#define PA_PWRMODEUSERDATA3 0x15B3
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#define PA_PWRMODEUSERDATA4 0x15B4
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#define PA_PWRMODEUSERDATA5 0x15B5
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#define PA_PWRMODEUSERDATA6 0x15B6
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#define PA_PWRMODEUSERDATA7 0x15B7
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#define PA_PWRMODEUSERDATA8 0x15B8
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#define PA_PWRMODEUSERDATA9 0x15B9
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#define PA_PWRMODEUSERDATA10 0x15BA
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#define PA_PWRMODEUSERDATA11 0x15BB
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#define PA_PACPFRAMECOUNT 0x15C0
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#define PA_PACPERRORCOUNT 0x15C1
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#define PA_PHYTESTCONTROL 0x15C2
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#define PA_TXHSG4SYNCLENGTH 0x15D0
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#define PA_PEERRXHSG4ADAPTINITIAL 0x15D3
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#define PA_TXHSADAPTTYPE 0x15D4
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#define PA_TXHSG5SYNCLENGTH 0x15D6
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#define PA_PEERRXHSG5ADAPTINITIAL 0x15D9
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#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE
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#define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF
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#define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0
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#define PA_TXEQG1SETTING 0x15E1
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#define PA_TXEQG2SETTING 0x15E2
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#define PA_TXEQG3SETTING 0x15E3
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#define PA_TXEQG4SETTING 0x15E4
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#define PA_TXEQG5SETTING 0x15E5
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#define PA_TXEQG6SETTING 0x15E6
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#define PA_TXEQTRSETTING 0x15E7
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#define PA_PEERTXEQTRSETTING 0x15E8
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#define PA_PRECODEEN 0x15E9
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#define PA_EQTR_GEAR 0x15EA
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#define PA_TXADAPTLENGTH_EQTR 0x15EB
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/* Adapt type for PA_TXHSADAPTTYPE attribute */
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#define PA_REFRESH_ADAPT 0x00
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#define PA_INITIAL_ADAPT 0x01
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#define PA_NO_ADAPT 0x03
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#define PA_TACTIVATE_TIME_UNIT_US 10
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#define PA_HIBERN8_TIME_UNIT_US 100
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/*Other attributes*/
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#define VS_POWERSTATE 0xD083
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#define VS_MPHYCFGUPDT 0xD085
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#define VS_DEBUGOMC 0xD09E
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#define VS_MPHYDISABLE 0xD0C1
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#define PA_GRANULARITY_MIN_VAL 1
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#define PA_GRANULARITY_MAX_VAL 6
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/* PHY Adapter Protocol Constants */
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#define PA_MAXDATALANES 4
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/*
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* TX EQTR's minimum TAdapt should not be less than 10us.
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* This value is rounded up into the nearest Unit Intervals (UI)
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*/
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#define TX_EQTR_HS_G4_MIN_T_ADAPT 166400
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#define TX_EQTR_HS_G5_MIN_T_ADAPT 332800
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#define TX_EQTR_HS_G6_MIN_T_ADAPT 262144
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#define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88
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#define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89
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#define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89
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#define TX_EQTR_CAP_MASK 0x7F
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#define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8
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#define TX_EQTR_ADAPT_RESERVED 0xFF
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#define TX_HS_NUM_PRESHOOT 8
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#define TX_HS_NUM_DEEMPHASIS 8
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#define TX_HS_PRESHOOT_SHIFT 4
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#define TX_HS_DEEMPHASIS_SHIFT 4
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#define TX_HS_PRESHOOT_OFFSET 0
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#define TX_HS_DEEMPHASIS_OFFSET 16
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#define TX_HS_PRESHOOT_LANE_SHIFT(lane) \
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(TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT)
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#define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \
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(TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT)
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#define TX_HS_PRESHOOT_BITS(lane, val) \
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((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane))
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#define TX_HS_DEEMPHASIS_BITS(lane, val) \
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((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane))
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#define RX_FOM_VALUE_MASK 0x7F
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#define RX_FOM_PRECODING_EN_BIT BIT(7)
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#define PRECODEEN_TX_OFFSET 0
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#define PRECODEEN_RX_OFFSET 4
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#define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane)))
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#define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane)))
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enum ufs_tx_eq_preset {
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UFS_TX_EQ_PRESET_P0,
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UFS_TX_EQ_PRESET_P1,
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UFS_TX_EQ_PRESET_P2,
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UFS_TX_EQ_PRESET_P3,
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UFS_TX_EQ_PRESET_P4,
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UFS_TX_EQ_PRESET_P5,
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UFS_TX_EQ_PRESET_P6,
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UFS_TX_EQ_PRESET_P7,
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UFS_TX_EQ_PRESET_MAX,
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};
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enum ufs_tx_hs_preshoot {
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UFS_TX_HS_PRESHOOT_DB_0P0,
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UFS_TX_HS_PRESHOOT_DB_0P4,
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UFS_TX_HS_PRESHOOT_DB_0P8,
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UFS_TX_HS_PRESHOOT_DB_1P2,
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UFS_TX_HS_PRESHOOT_DB_1P6,
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UFS_TX_HS_PRESHOOT_DB_2P5,
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UFS_TX_HS_PRESHOOT_DB_3P5,
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UFS_TX_HS_PRESHOOT_DB_4P7,
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};
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enum ufs_tx_hs_deemphasis {
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UFS_TX_HS_DEEMPHASIS_DB_0P0,
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UFS_TX_HS_DEEMPHASIS_DB_0P8,
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UFS_TX_HS_DEEMPHASIS_DB_1P6,
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UFS_TX_HS_DEEMPHASIS_DB_2P5,
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UFS_TX_HS_DEEMPHASIS_DB_3P5,
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UFS_TX_HS_DEEMPHASIS_DB_4P7,
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UFS_TX_HS_DEEMPHASIS_DB_6P0,
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UFS_TX_HS_DEEMPHASIS_DB_7P6,
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};
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enum ufs_eom_eye_mask {
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UFS_EOM_EYE_MASK_M,
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UFS_EOM_EYE_MASK_L,
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UFS_EOM_EYE_MASK_U,
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};
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#define DL_FC0ProtectionTimeOutVal_Default 8191
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#define DL_TC0ReplayTimeOutVal_Default 65535
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#define DL_AFC0ReqTimeOutVal_Default 32767
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#define DL_FC1ProtectionTimeOutVal_Default 8191
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#define DL_TC1ReplayTimeOutVal_Default 65535
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#define DL_AFC1ReqTimeOutVal_Default 32767
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#define DME_LocalFC0ProtectionTimeOutVal 0xD041
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#define DME_LocalTC0ReplayTimeOutVal 0xD042
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#define DME_LocalAFC0ReqTimeOutVal 0xD043
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enum ufs_op_mode {
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LS_MODE = 1,
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HS_MODE = 2,
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};
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/* PA power modes */
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enum ufs_pa_pwr_mode {
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FAST_MODE = 1,
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SLOW_MODE = 2,
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FASTAUTO_MODE = 4,
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SLOWAUTO_MODE = 5,
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UNCHANGED = 7,
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};
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#define PWRMODE_MASK 0xF
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#define PWRMODE_RX_OFFSET 4
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/* PA TX/RX Frequency Series */
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enum ufs_hs_gear_rate {
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PA_HS_MODE_A = 1,
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PA_HS_MODE_B = 2,
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};
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enum ufs_pwm_gear_tag {
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UFS_PWM_DONT_CHANGE, /* Don't change Gear */
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UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
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UFS_PWM_G2, /* PWM Gear 2 */
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UFS_PWM_G3, /* PWM Gear 3 */
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UFS_PWM_G4, /* PWM Gear 4 */
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UFS_PWM_G5, /* PWM Gear 5 */
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UFS_PWM_G6, /* PWM Gear 6 */
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UFS_PWM_G7, /* PWM Gear 7 */
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};
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enum ufs_hs_gear_tag {
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UFS_HS_DONT_CHANGE, /* Don't change Gear */
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UFS_HS_G1, /* HS Gear 1 (default for reset) */
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UFS_HS_G2, /* HS Gear 2 */
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UFS_HS_G3, /* HS Gear 3 */
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UFS_HS_G4, /* HS Gear 4 */
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UFS_HS_G5, /* HS Gear 5 */
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UFS_HS_G6, /* HS Gear 6 */
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UFS_HS_GEAR_MAX = UFS_HS_G6,
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};
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enum ufs_lanes {
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UFS_LANE_DONT_CHANGE, /* Don't change Lane */
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UFS_LANE_1, /* Lane 1 (default for reset) */
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UFS_LANE_2, /* Lane 2 */
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};
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enum ufs_unipro_ver {
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UFS_UNIPRO_VER_RESERVED = 0,
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UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
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UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
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UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
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UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
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UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
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UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
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/* UniPro version field mask in PA_LOCALVERINFO */
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UFS_UNIPRO_VER_MASK = 0xF,
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};
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/*
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* Data Link Layer Attributes
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|
*/
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#define DL_TXPREEMPTIONCAP 0x2000
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#define DL_TC0TXMAXSDUSIZE 0x2001
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#define DL_TC0RXINITCREDITVAL 0x2002
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#define DL_TC1TXMAXSDUSIZE 0x2003
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#define DL_TC1RXINITCREDITVAL 0x2004
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|
#define DL_TC0TXBUFFERSIZE 0x2005
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|
#define DL_TC1TXBUFFERSIZE 0x2006
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|
#define DL_TC0TXFCTHRESHOLD 0x2040
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|
#define DL_FC0PROTTIMEOUTVAL 0x2041
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|
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
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|
#define DL_AFC0REQTIMEOUTVAL 0x2043
|
|
#define DL_AFC0CREDITTHRESHOLD 0x2044
|
|
#define DL_TC0OUTACKTHRESHOLD 0x2045
|
|
#define DL_PEERTC0PRESENT 0x2046
|
|
#define DL_PEERTC0RXINITCREVAL 0x2047
|
|
#define DL_TC1TXFCTHRESHOLD 0x2060
|
|
#define DL_FC1PROTTIMEOUTVAL 0x2061
|
|
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
|
|
#define DL_AFC1REQTIMEOUTVAL 0x2063
|
|
#define DL_AFC1CREDITTHRESHOLD 0x2064
|
|
#define DL_TC1OUTACKTHRESHOLD 0x2065
|
|
#define DL_PEERTC1PRESENT 0x2066
|
|
#define DL_PEERTC1RXINITCREVAL 0x2067
|
|
|
|
/*
|
|
* Network Layer Attributes
|
|
*/
|
|
#define N_DEVICEID 0x3000
|
|
#define N_DEVICEID_VALID 0x3001
|
|
#define N_TC0TXMAXSDUSIZE 0x3020
|
|
#define N_TC1TXMAXSDUSIZE 0x3021
|
|
|
|
/*
|
|
* Transport Layer Attributes
|
|
*/
|
|
#define T_NUMCPORTS 0x4000
|
|
#define T_NUMTESTFEATURES 0x4001
|
|
#define T_CONNECTIONSTATE 0x4020
|
|
#define T_PEERDEVICEID 0x4021
|
|
#define T_PEERCPORTID 0x4022
|
|
#define T_TRAFFICCLASS 0x4023
|
|
#define T_PROTOCOLID 0x4024
|
|
#define T_CPORTFLAGS 0x4025
|
|
#define T_TXTOKENVALUE 0x4026
|
|
#define T_RXTOKENVALUE 0x4027
|
|
#define T_LOCALBUFFERSPACE 0x4028
|
|
#define T_PEERBUFFERSPACE 0x4029
|
|
#define T_CREDITSTOSEND 0x402A
|
|
#define T_CPORTMODE 0x402B
|
|
#define T_TC0TXMAXSDUSIZE 0x4060
|
|
#define T_TC1TXMAXSDUSIZE 0x4061
|
|
|
|
/* CPort setting */
|
|
#define E2EFC_ON (1 << 0)
|
|
#define E2EFC_OFF (0 << 0)
|
|
#define CSD_N_ON (0 << 1)
|
|
#define CSD_N_OFF (1 << 1)
|
|
#define CSV_N_ON (0 << 2)
|
|
#define CSV_N_OFF (1 << 2)
|
|
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
|
|
|
|
/* CPort connection state */
|
|
enum {
|
|
CPORT_IDLE = 0,
|
|
CPORT_CONNECTED,
|
|
};
|
|
|
|
#endif /* _UNIPRO_H_ */
|