mirror of
https://github.com/torvalds/linux.git
synced 2026-05-31 10:33:41 +02:00
4a09126a33
Add defines for the pixel clock sampling modes (rising edge, falling edge, dual edge) for parallel video interfaces. This avoids hardcoded constants in device tree sources. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
28 lines
889 B
C
28 lines
889 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
|
/*
|
|
* Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
|
*/
|
|
|
|
#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
|
|
#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
|
|
|
|
#define MEDIA_BUS_TYPE_CSI2_CPHY 1
|
|
#define MEDIA_BUS_TYPE_CSI1 2
|
|
#define MEDIA_BUS_TYPE_CCP2 3
|
|
#define MEDIA_BUS_TYPE_CSI2_DPHY 4
|
|
#define MEDIA_BUS_TYPE_PARALLEL 5
|
|
#define MEDIA_BUS_TYPE_BT656 6
|
|
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC 0
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB 1
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC 2
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA 3
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4
|
|
#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5
|
|
|
|
#define MEDIA_PCLK_SAMPLE_FALLING_EDGE 0
|
|
#define MEDIA_PCLK_SAMPLE_RISING_EDGE 1
|
|
#define MEDIA_PCLK_SAMPLE_DUAL_EDGE 2
|
|
|
|
#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
|