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f390a1fac1
Add device tree bindings for the global clock controller on Qualcomm Shikra SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
264 lines
9.2 KiB
C
264 lines
9.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
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/* GCC clocks */
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#define GPLL0 0
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#define GPLL0_OUT_AUX2 1
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#define GPLL1 2
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#define GPLL10 3
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#define GPLL11 4
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#define GPLL12 5
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#define GPLL12_OUT_AUX2 6
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#define GPLL3 7
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#define GPLL3_OUT_MAIN 8
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#define GPLL4 9
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#define GPLL5 10
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#define GPLL6 11
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#define GPLL6_OUT_MAIN 12
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#define GPLL7 13
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#define GPLL8 14
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#define GPLL8_OUT_MAIN 15
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#define GPLL9 16
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#define GPLL9_OUT_MAIN 17
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#define GCC_AHB2PHY_CSI_CLK 18
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#define GCC_AHB2PHY_USB_CLK 19
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#define GCC_BOOT_ROM_AHB_CLK 20
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#define GCC_CAM_THROTTLE_NRT_CLK 21
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#define GCC_CAM_THROTTLE_RT_CLK 22
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#define GCC_CAMERA_AHB_CLK 23
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#define GCC_CAMERA_XO_CLK 24
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#define GCC_CAMSS_AXI_CLK 25
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#define GCC_CAMSS_AXI_CLK_SRC 26
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#define GCC_CAMSS_CAMNOC_ATB_CLK 27
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#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28
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#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29
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#define GCC_CAMSS_CCI_0_CLK 30
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#define GCC_CAMSS_CCI_CLK_SRC 31
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#define GCC_CAMSS_CPHY_0_CLK 32
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#define GCC_CAMSS_CPHY_1_CLK 33
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 34
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#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 36
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#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37
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#define GCC_CAMSS_MCLK0_CLK 38
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#define GCC_CAMSS_MCLK0_CLK_SRC 39
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#define GCC_CAMSS_MCLK1_CLK 40
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#define GCC_CAMSS_MCLK1_CLK_SRC 41
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#define GCC_CAMSS_MCLK2_CLK 42
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#define GCC_CAMSS_MCLK2_CLK_SRC 43
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#define GCC_CAMSS_MCLK3_CLK 44
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#define GCC_CAMSS_MCLK3_CLK_SRC 45
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#define GCC_CAMSS_NRT_AXI_CLK 46
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#define GCC_CAMSS_OPE_AHB_CLK 47
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#define GCC_CAMSS_OPE_AHB_CLK_SRC 48
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#define GCC_CAMSS_OPE_CLK 49
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#define GCC_CAMSS_OPE_CLK_SRC 50
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#define GCC_CAMSS_RT_AXI_CLK 51
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#define GCC_CAMSS_TFE_0_CLK 52
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#define GCC_CAMSS_TFE_0_CLK_SRC 53
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#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54
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#define GCC_CAMSS_TFE_0_CSID_CLK 55
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#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56
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#define GCC_CAMSS_TFE_1_CLK 57
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#define GCC_CAMSS_TFE_1_CLK_SRC 58
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#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59
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#define GCC_CAMSS_TFE_1_CSID_CLK 60
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#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61
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#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62
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#define GCC_CAMSS_TOP_AHB_CLK 63
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#define GCC_CAMSS_TOP_AHB_CLK_SRC 64
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#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66
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#define GCC_DDRSS_GPU_AXI_CLK 67
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#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68
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#define GCC_DISP_AHB_CLK 69
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#define GCC_DISP_GPLL0_CLK_SRC 70
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 71
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#define GCC_DISP_HF_AXI_CLK 72
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#define GCC_DISP_THROTTLE_CORE_CLK 73
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#define GCC_DISP_XO_CLK 74
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#define GCC_EMAC0_AHB_CLK 75
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#define GCC_EMAC0_AXI_CLK 76
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#define GCC_EMAC0_AXI_CLK_SRC 77
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#define GCC_EMAC0_AXI_SYS_NOC_CLK 78
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#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79
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#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80
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#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81
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#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82
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#define GCC_EMAC0_PHY_AUX_CLK 83
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#define GCC_EMAC0_PHY_AUX_CLK_SRC 84
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#define GCC_EMAC0_PTP_CLK 85
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#define GCC_EMAC0_PTP_CLK_SRC 86
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#define GCC_EMAC0_RGMII_CLK 87
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#define GCC_EMAC0_RGMII_CLK_SRC 88
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#define GCC_EMAC1_AHB_CLK 89
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#define GCC_EMAC1_AXI_CLK 90
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#define GCC_EMAC1_AXI_CLK_SRC 91
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#define GCC_EMAC1_AXI_SYS_NOC_CLK 92
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#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93
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#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94
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#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95
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#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96
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#define GCC_EMAC1_PHY_AUX_CLK 97
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#define GCC_EMAC1_PHY_AUX_CLK_SRC 98
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#define GCC_EMAC1_PTP_CLK 99
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#define GCC_EMAC1_PTP_CLK_SRC 100
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#define GCC_EMAC1_RGMII_CLK 101
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#define GCC_EMAC1_RGMII_CLK_SRC 102
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#define GCC_GP1_CLK 103
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#define GCC_GP1_CLK_SRC 104
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#define GCC_GP2_CLK 105
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#define GCC_GP2_CLK_SRC 106
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#define GCC_GP3_CLK 107
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#define GCC_GP3_CLK_SRC 108
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#define GCC_GPU_CFG_AHB_CLK 109
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#define GCC_GPU_GPLL0_CLK_SRC 110
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 111
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#define GCC_GPU_IREF_CLK 112
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#define GCC_GPU_MEMNOC_GFX_CLK 113
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#define GCC_GPU_SMMU_VOTE_CLK 114
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#define GCC_GPU_SNOC_DVM_GFX_CLK 115
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#define GCC_GPU_THROTTLE_CORE_CLK 116
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#define GCC_LPASS_CONFIG_CLK 117
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#define GCC_LPASS_CORE_AXIM_CLK 118
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#define GCC_MMU_TCU_VOTE_CLK 119
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#define GCC_PCIE_AUX_CLK 120
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#define GCC_PCIE_AUX_CLK_SRC 121
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#define GCC_PCIE_AUX_PHY_CLK_SRC 122
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#define GCC_PCIE_CFG_AHB_CLK 123
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#define GCC_PCIE_CLKREF_EN 124
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#define GCC_PCIE_MSTR_AXI_CLK 125
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#define GCC_PCIE_PIPE_CLK 126
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#define GCC_PCIE_PIPE_CLK_SRC 127
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#define GCC_PCIE_RCHNG_PHY_CLK 128
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#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129
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#define GCC_PCIE_SLEEP_CLK 130
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#define GCC_PCIE_SLV_AXI_CLK 131
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#define GCC_PCIE_SLV_Q2A_AXI_CLK 132
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#define GCC_PCIE_TBU_CLK 133
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#define GCC_PCIE_THROTTLE_CORE_CLK 134
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#define GCC_PCIE_THROTTLE_XO_CLK 135
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#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136
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#define GCC_PDM2_CLK 137
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#define GCC_PDM2_CLK_SRC 138
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#define GCC_PDM_AHB_CLK 139
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#define GCC_PDM_XO4_CLK 140
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#define GCC_PWM0_XO512_CLK 141
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 143
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#define GCC_QMIP_DISP_AHB_CLK 144
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#define GCC_QMIP_GPU_CFG_AHB_CLK 145
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#define GCC_QMIP_PCIE_CFG_AHB_CLK 146
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148
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#define GCC_QUPV3_WRAP0_CORE_CLK 149
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#define GCC_QUPV3_WRAP0_S0_CLK 150
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151
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#define GCC_QUPV3_WRAP0_S1_CLK 152
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153
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#define GCC_QUPV3_WRAP0_S2_CLK 154
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155
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#define GCC_QUPV3_WRAP0_S3_CLK 156
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157
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#define GCC_QUPV3_WRAP0_S4_CLK 158
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159
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#define GCC_QUPV3_WRAP0_S5_CLK 160
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161
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#define GCC_QUPV3_WRAP0_S6_CLK 162
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163
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#define GCC_QUPV3_WRAP0_S7_CLK 164
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165
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#define GCC_QUPV3_WRAP0_S8_CLK 166
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#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167
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#define GCC_QUPV3_WRAP0_S9_CLK 168
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#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171
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#define GCC_SDCC1_AHB_CLK 172
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#define GCC_SDCC1_APPS_CLK 173
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#define GCC_SDCC1_APPS_CLK_SRC 174
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#define GCC_SDCC1_ICE_CORE_CLK 175
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 176
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#define GCC_SDCC2_AHB_CLK 177
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#define GCC_SDCC2_APPS_CLK 178
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#define GCC_SDCC2_APPS_CLK_SRC 179
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 180
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#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181
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#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182
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#define GCC_TSCSS_AHB_CLK 183
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#define GCC_TSCSS_CLK_SRC 184
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#define GCC_TSCSS_CNTR_CLK 185
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#define GCC_TSCSS_ETU_CLK 186
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#define GCC_UFS_CLKREF_EN 187
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#define GCC_USB20_MASTER_CLK 188
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#define GCC_USB20_MASTER_CLK_SRC 189
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#define GCC_USB20_MOCK_UTMI_CLK 190
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#define GCC_USB20_MOCK_UTMI_CLK_SRC 191
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#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192
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#define GCC_USB20_SLEEP_CLK 193
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#define GCC_USB30_PRIM_MASTER_CLK 194
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 195
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198
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#define GCC_USB30_PRIM_SLEEP_CLK 199
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#define GCC_USB3_PRIM_CLKREF_EN 200
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 203
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204
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#define GCC_VCODEC0_AXI_CLK 205
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#define GCC_VENUS_AHB_CLK 206
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#define GCC_VENUS_CTL_AXI_CLK 207
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#define GCC_VIDEO_AHB_CLK 208
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#define GCC_VIDEO_AXI0_CLK 209
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#define GCC_VIDEO_THROTTLE_CORE_CLK 210
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#define GCC_VIDEO_VCODEC0_SYS_CLK 211
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#define GCC_VIDEO_VENUS_CLK_SRC 212
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#define GCC_VIDEO_VENUS_CTL_CLK 213
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#define GCC_VIDEO_XO_CLK 214
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/* GCC power domains */
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#define GCC_CAMSS_TOP_GDSC 0
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#define GCC_EMAC0_GDSC 1
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#define GCC_EMAC1_GDSC 2
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#define GCC_PCIE_GDSC 3
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#define GCC_USB20_GDSC 4
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#define GCC_USB30_PRIM_GDSC 5
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#define GCC_VCODEC0_GDSC 6
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#define GCC_VENUS_GDSC 7
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/* GCC resets */
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#define GCC_CAMSS_OPE_BCR 0
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#define GCC_CAMSS_TFE_BCR 1
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#define GCC_CAMSS_TOP_BCR 2
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#define GCC_EMAC0_BCR 3
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#define GCC_EMAC1_BCR 4
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#define GCC_GPU_BCR 5
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#define GCC_MMSS_BCR 6
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#define GCC_PCIE_BCR 7
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#define GCC_PCIE_PHY_BCR 8
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#define GCC_PDM_BCR 9
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#define GCC_QUPV3_WRAPPER_0_BCR 10
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#define GCC_QUSB2PHY_PRIM_BCR 11
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#define GCC_QUSB2PHY_SEC_BCR 12
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#define GCC_SDCC1_BCR 13
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#define GCC_SDCC2_BCR 14
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#define GCC_TSCSS_BCR 15
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#define GCC_USB20_BCR 16
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#define GCC_USB30_PRIM_BCR 17
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18
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#define GCC_USB3_DP_PHY_PRIM_BCR 19
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#define GCC_USB3_PHY_PRIM_SP0_BCR 20
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 21
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#define GCC_VCODEC0_BCR 22
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#define GCC_VENUS_BCR 23
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#define GCC_VIDEO_INTERFACE_BCR 24
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#endif
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