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58410321db
Add device tree bindings for the video clock controller on Qualcomm Maili SoC. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260717-maili_videocc-v3-1-6656694b06a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_AHB_CLK 0
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#define VIDEO_CC_AHB_CLK_SRC 1
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#define VIDEO_CC_MVS0_CLK 2
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#define VIDEO_CC_MVS0_CLK_SRC 3
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#define VIDEO_CC_MVS0_FREERUN_CLK 4
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#define VIDEO_CC_MVS0_SHIFT_CLK 5
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#define VIDEO_CC_MVS0_VPP0_CLK 6
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#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7
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#define VIDEO_CC_MVS0B_CLK 8
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#define VIDEO_CC_MVS0B_CLK_SRC 9
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#define VIDEO_CC_MVS0B_FREERUN_CLK 10
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#define VIDEO_CC_MVS0C_CLK 11
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#define VIDEO_CC_MVS0C_CLK_SRC 12
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#define VIDEO_CC_MVS0C_DEBUG_CLK 13
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#define VIDEO_CC_MVS0C_FREERUN_CLK 14
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#define VIDEO_CC_MVS0C_SHIFT_CLK 15
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#define VIDEO_CC_PLL0 16
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#define VIDEO_CC_PLL1 17
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#define VIDEO_CC_PLL2 18
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#define VIDEO_CC_SLEEP_CLK 19
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#define VIDEO_CC_TS_XO_CLK 20
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#define VIDEO_CC_XO_CLK 21
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#define VIDEO_CC_XO_CLK_SRC 22
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/* VIDEO_CC power domains */
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#define VIDEO_CC_MVS0_GDSC 0
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#define VIDEO_CC_MVS0_VPP0_GDSC 1
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#define VIDEO_CC_MVS0C_GDSC 2
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/* VIDEO_CC resets */
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#define VIDEO_CC_INTERFACE_BCR 0
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#define VIDEO_CC_MVS0_BCR 1
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#define VIDEO_CC_MVS0_CLK_ARES 2
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#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 3
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#define VIDEO_CC_MVS0_VPP0_BCR 4
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#define VIDEO_CC_MVS0C_BCR 5
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#define VIDEO_CC_MVS0C_CLK_ARES 6
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#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 7
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#define VIDEO_CC_XO_CLK_ARES 8
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#endif
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