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Export cxl core functions for a Type2 driver being able to discover and map the device registers. Signed-off-by: Alejandro Lucero <alucerop@amd.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com> Acked-by: Edward Cree <ecree.xilinx@gmail.com> Link: https://patch.msgid.link/20260629183727.51502-2-alejandro.lucero-palau@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
23 lines
531 B
C
23 lines
531 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_CXL_PCI_H__
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#define __CXL_CXL_PCI_H__
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_PMU,
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CXL_REGLOC_RBI_TYPES
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};
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struct cxl_register_map;
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struct pci_dev;
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int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
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struct cxl_register_map *map);
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#endif
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