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a28de63356
The Microchip USB3340x ULPI PHY requires a delay when switching to the
high-speed transmitter. See:
http://ww1.microchip.com/downloads/en/DeviceDoc/80000645A.pdf
Module 2 "Device Enumeration Failure with Link IP Systems"
For details on the behavior and fix, refer to the AMD (formerly Xilinx)
forum post: "USB stuck in full speed mode with USB3340 ULPI PHY, ZynqMP."
This patch uses the USB PHY Vendor-ID and Product-ID to detect the
USB3340 PHY and then applies the necessary fix if this PHY is found.
Signed-off-by: Ingo Rohloff <ingo.rohloff@lauterbach.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://patch.msgid.link/20260305121452.54082-2-ingo.rohloff@lauterbach.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
130 lines
2.7 KiB
C
130 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
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*
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* Copyright (C) 2015 Intel Corporation
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*
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* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
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*/
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#include <linux/delay.h>
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#include <linux/time64.h>
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#include <linux/ulpi/regs.h>
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#include <linux/ulpi/driver.h>
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#include "core.h"
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#include "io.h"
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#define USB_VENDOR_MICROCHIP 0x0424
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#define DWC3_ULPI_ADDR(a) \
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((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
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DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
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DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
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#define DWC3_ULPI_BASE_DELAY DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
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static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
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{
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unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
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unsigned int count = 10000;
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u32 reg;
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if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
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ns += DWC3_ULPI_BASE_DELAY;
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if (read)
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ns += DWC3_ULPI_BASE_DELAY;
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reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
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if (reg & DWC3_GUSB2PHYCFG_SUSPHY)
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usleep_range(1000, 1200);
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while (count--) {
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ndelay(ns);
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reg = dwc3_readl(dwc, DWC3_GUSB2PHYACC(0));
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if (reg & DWC3_GUSB2PHYACC_DONE)
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static int dwc3_ulpi_read(struct device *dev, u8 addr)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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u32 reg;
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int ret;
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reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
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dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg);
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ret = dwc3_ulpi_busyloop(dwc, addr, true);
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if (ret)
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return ret;
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reg = dwc3_readl(dwc, DWC3_GUSB2PHYACC(0));
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return DWC3_GUSB2PHYACC_DATA(reg);
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}
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static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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u32 reg;
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reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
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reg |= DWC3_GUSB2PHYACC_WRITE | val;
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dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg);
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return dwc3_ulpi_busyloop(dwc, addr, false);
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}
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static const struct ulpi_ops dwc3_ulpi_ops = {
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.read = dwc3_ulpi_read,
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.write = dwc3_ulpi_write,
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};
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static void dwc3_ulpi_detect_config(struct dwc3 *dwc)
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{
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struct ulpi *ulpi = dwc->ulpi;
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switch (ulpi->id.vendor) {
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case USB_VENDOR_MICROCHIP:
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switch (ulpi->id.product) {
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case 0x0009:
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/* Microchip USB3340 ULPI PHY */
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dwc->enable_usb2_transceiver_delay = true;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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int dwc3_ulpi_init(struct dwc3 *dwc)
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{
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/* Register the interface */
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dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
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if (IS_ERR(dwc->ulpi)) {
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dev_err(dwc->dev, "failed to register ULPI interface");
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return PTR_ERR(dwc->ulpi);
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}
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dwc3_ulpi_detect_config(dwc);
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return 0;
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}
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void dwc3_ulpi_exit(struct dwc3 *dwc)
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{
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if (dwc->ulpi) {
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ulpi_unregister_interface(dwc->ulpi);
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dwc->ulpi = NULL;
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}
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}
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