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8f18d3cbd9
Add support for RZ/G3L RSCI. The RSCI IP found on the RZ/G3L SoC is similar to RZ/G3E, but it has 3 clocks (2 module clocks + 1 external clock) instead of 6 clocks (5 module clocks + 1 external clock) on the RZ/G3E. Both RZ/G3L and RZ/G3E have a 32-bit FIFO, but RZ/G3L has a single TCLK with internal dividers, whereas the RZ/G3E has explicit clocks for TCLK and its dividers. Add a new port type RSCI_PORT_SCIF32_SINGLE_TCLK to handle this clock difference. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260312082708.98835-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 lines
270 B
C
13 lines
270 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RSCI_H__
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#define __RSCI_H__
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#include "sh-sci-common.h"
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extern struct sci_of_data of_rsci_rzg3e_data;
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extern struct sci_of_data of_rsci_rzg3l_data;
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extern struct sci_of_data of_rsci_rzt2h_data;
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#endif /* __RSCI_H__ */
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