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Add support for ADC_TM part of PMIC5 Gen3 in an auxiliary driver under the Gen3 ADC driver. Its functionality is similar to that of PMIC5 Gen2 ADC_TM, which implements the threshold setting and interrupt generating functions, used to support thermal trip points. In Gen3 ADC, the register interface is implemented on one or more SDAM (Shared Direct Access Memory) peripherals instead of dedicated ADC peripherals. Each ADC SDAM has eight channels which can be configured for either immediate reads (main ADC driver's functionality) or ADC_TM reads. By convention, the first channel of the first ADC SDAM is reserved for all immediate reads and remaining channels across all SDAMs are used for ADC_TM functionality. On the first SDAM, the interrupt line and configuration registers are shared between the main ADC and auxiliary ADC_TM drivers. Access to the registers is protected through a mutex shared between the drivers. The ADC_TM driver accesses this mutex and some other functions shared from the main driver (like adc5_gen3_get_scaled_reading() for immediate channel reads in the .get_temp() callback) through APIs exported into a shared namespace. Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://patch.msgid.link/20260722-gen3_adc_tm-v4-3-011981f756c8@oss.qualcomm.com
68 lines
2.8 KiB
Plaintext
68 lines
2.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config QCOM_TSENS
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tristate "Qualcomm TSENS Temperature Alarm"
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depends on NVMEM_QCOM_QFPROM
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depends on ARCH_QCOM || COMPILE_TEST
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help
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This enables the thermal sysfs driver for the TSENS device. It shows
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up in Sysfs as a thermal zone with multiple trip points. Disabling the
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thermal zone device via the mode file results in disabling the sensor.
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Also able to set threshold temperature for both hot and cold and update
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when a threshold is reached.
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config QCOM_SPMI_ADC_TM5
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tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5"
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depends on OF && SPMI && IIO
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select REGMAP_SPMI
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select QCOM_VADC_COMMON
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help
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This enables the thermal driver for the ADC thermal monitoring
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device. It shows up as a thermal zone with multiple trip points.
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Thermal client sets threshold temperature for both warm and cool and
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gets updated when a threshold is reached.
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config QCOM_SPMI_MBG_TM
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tristate "Qualcomm SPMI PMIC MBG Temperature monitor"
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depends on QCOM_SPMI_ADC5_GEN3
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select REGMAP_SPMI
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help
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This enables Qualcomm PMIC MBG (Master Bandgap) thermal monitor.
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The MBG block monitors PMIC die temperature in hardware and raises an
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interrupt when the programmed threshold is crossed.
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Temperature is read from the associated ADC channel, and threshold
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interrupts are forwarded to the thermal framework as trip-violation
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events. Current support handles a single LVL1 upper (hot) trip.
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config QCOM_SPMI_ADC_TM5_GEN3
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tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3"
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depends on QCOM_SPMI_ADC5_GEN3
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help
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This enables the auxiliary thermal driver for the ADC5 Gen3 thermal
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monitoring device. It shows up as a thermal zone with multiple trip points.
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Thermal client sets threshold temperature for both warm and cool and
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gets updated when a threshold is reached.
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config QCOM_SPMI_TEMP_ALARM
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tristate "Qualcomm SPMI PMIC Temperature Alarm"
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depends on OF && SPMI && IIO
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select REGMAP_SPMI
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help
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This enables a thermal sysfs driver for Qualcomm plug-and-play (QPNP)
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PMIC devices. It shows up in sysfs as a thermal sensor with multiple
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trip points. The temperature reported by the thermal sensor reflects the
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real time die temperature if an ADC is present or an estimate of the
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temperature based upon the over temperature stage value.
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config QCOM_LMH
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tristate "Qualcomm Limits Management Hardware"
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depends on ARCH_QCOM || COMPILE_TEST
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select QCOM_SCM
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help
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This enables initialization of Qualcomm limits management
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hardware(LMh). LMh allows for hardware-enforced mitigation for cpus based on
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input from temperature and current sensors. On many newer Qualcomm SoCs
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LMh is configured in the firmware and this feature need not be enabled.
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However, on certain SoCs like sdm845 LMh has to be configured from kernel.
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