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eaf84ff673
The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
that line is muxed for IRQ triggering (muxval 6), but only if it's
explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
behaviour, so we added a optional workaround, triggered by a quirk bit,
which triggers remuxing the pin when it's configured for IRQ, while we
need to read its value.
For some reasons this quirk flag was copied over to newer SoCs, even
though they don't show this behaviour, and the GPIO data register
reflects the true GPIO state even with a pin muxed to IRQ trigger.
Remove the unneeded quirk from the A523 family, where it's definitely
not needed (confirmed by experiments), and where it actually breaks,
because the workaround is not compatible with the newer generation
pinctrl IP used in that chip.
Together with a DT change this fixes GPIO IRQ operation on the A523
family of SoCs, as for instance used for the SD card detection.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes:
|
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|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| pinctrl-sun4i-a10.c | ||
| pinctrl-sun5i.c | ||
| pinctrl-sun6i-a31-r.c | ||
| pinctrl-sun6i-a31.c | ||
| pinctrl-sun8i-a23-r.c | ||
| pinctrl-sun8i-a23.c | ||
| pinctrl-sun8i-a33.c | ||
| pinctrl-sun8i-a83t-r.c | ||
| pinctrl-sun8i-a83t.c | ||
| pinctrl-sun8i-h3-r.c | ||
| pinctrl-sun8i-h3.c | ||
| pinctrl-sun8i-v3s.c | ||
| pinctrl-sun9i-a80-r.c | ||
| pinctrl-sun9i-a80.c | ||
| pinctrl-sun20i-d1.c | ||
| pinctrl-sun50i-a64-r.c | ||
| pinctrl-sun50i-a64.c | ||
| pinctrl-sun50i-a100-r.c | ||
| pinctrl-sun50i-a100.c | ||
| pinctrl-sun50i-h5.c | ||
| pinctrl-sun50i-h6-r.c | ||
| pinctrl-sun50i-h6.c | ||
| pinctrl-sun50i-h616-r.c | ||
| pinctrl-sun50i-h616.c | ||
| pinctrl-sun55i-a523-r.c | ||
| pinctrl-sun55i-a523.c | ||
| pinctrl-suniv-f1c100s.c | ||
| pinctrl-sunxi-dt.c | ||
| pinctrl-sunxi.c | ||
| pinctrl-sunxi.h | ||