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486a70ef84
The comment in the mtk_phy_tmds_clk_ratio() function clearly and
correctly explains that the TMDS ratio has to be 1/10 for data
rates under 3.4Gbps, and 1/40 over that.
Unfortunately though, the TXC_DIV register setting was wrong, as
in value 3 means to divide by 8 and, in order to achieve the in
spec 1/40 (tmds) data rate, this has to divide by 4 instead!
Add definitions for the TXC_DIV register values clearly explaining
the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
value to the register in mtk_phy_tmds_clk_ratio().
This fixes out of spec clocking and, with this change, SoCs using
the MT8195 class HDMI PHYs can now successfully be configured to
output 3840x2160@60Hz over HDMI.
Fixes:
|
||
|---|---|---|
| .. | ||
| Kconfig | ||
| Makefile | ||
| phy-mtk-dp.c | ||
| phy-mtk-hdmi-mt2701.c | ||
| phy-mtk-hdmi-mt8173.c | ||
| phy-mtk-hdmi-mt8195.c | ||
| phy-mtk-hdmi-mt8195.h | ||
| phy-mtk-hdmi.c | ||
| phy-mtk-hdmi.h | ||
| phy-mtk-io.h | ||
| phy-mtk-mipi-csi-0-5-rx-reg.h | ||
| phy-mtk-mipi-csi-0-5.c | ||
| phy-mtk-mipi-dsi-mt8173.c | ||
| phy-mtk-mipi-dsi-mt8183.c | ||
| phy-mtk-mipi-dsi-mt8196.c | ||
| phy-mtk-mipi-dsi.c | ||
| phy-mtk-mipi-dsi.h | ||
| phy-mtk-pcie.c | ||
| phy-mtk-tphy.c | ||
| phy-mtk-ufs.c | ||
| phy-mtk-xfi-tphy.c | ||
| phy-mtk-xsphy.c | ||