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MediaTek has asked to switch from the ISC license to BSD-3-Clause-Clear, in order to improve clarity and the legal integrity of the code. The BSD-3-Clause license includes the "no endorsement" clause, which is important for protecting the reputation of the original authors and contributors by preventing unauthorized use of their names for endorsement purposes. This clause is absent in the BSD-2-Clause license, which is more permissive but lacks this specific protection. This change also cleans up the license of some Kconfig/Makefile files, which were accidentally marked as GPL. The GPL 2.0 remains in use on mt76x0, as well as two source files in mt7615 for which the license situation still needs to be clarified. Link: https://patch.msgid.link/20251008104250.46292-2-nbd@nbd.name Signed-off-by: Felix Fietkau <nbd@nbd.name>
205 lines
5.7 KiB
C
205 lines
5.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
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*/
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#include "mt76x2.h"
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#include "eeprom.h"
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#include "../mt76x02_phy.h"
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int mt76x2_set_sar_specs(struct ieee80211_hw *hw,
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const struct cfg80211_sar_specs *sar)
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{
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int err = -EINVAL, power = hw->conf.power_level * 2;
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struct mt76x02_dev *dev = hw->priv;
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struct mt76_phy *mphy = &dev->mphy;
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mutex_lock(&dev->mt76.mutex);
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if (!cfg80211_chandef_valid(&mphy->chandef))
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goto out;
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err = mt76_init_sar_power(hw, sar);
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if (err)
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goto out;
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dev->txpower_conf = mt76_get_sar_power(mphy, mphy->chandef.chan,
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power);
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/* convert to per-chain power for 2x2 devices */
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dev->txpower_conf -= 6;
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if (test_bit(MT76_STATE_RUNNING, &mphy->state))
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mt76x2_phy_set_txpower(dev);
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out:
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mutex_unlock(&dev->mt76.mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(mt76x2_set_sar_specs);
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static void
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mt76x2_set_wlan_state(struct mt76x02_dev *dev, bool enable)
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{
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u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
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if (enable)
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val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
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MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
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else
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val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
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MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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}
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void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable)
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{
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u32 val;
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if (!enable)
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goto out;
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val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
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val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
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if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
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val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
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}
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mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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out:
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mt76x2_set_wlan_state(dev, enable);
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}
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EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
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void mt76_write_mac_initvals(struct mt76x02_dev *dev)
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{
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#define DEFAULT_PROT_CFG_CCK \
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(FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \
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FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
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FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
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MT_PROT_CFG_RTS_THRESH)
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#define DEFAULT_PROT_CFG_OFDM \
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(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
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FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
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FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
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MT_PROT_CFG_RTS_THRESH)
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#define DEFAULT_PROT_CFG_20 \
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(FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
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FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
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FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
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FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
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#define DEFAULT_PROT_CFG_40 \
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(FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
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FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
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FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
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FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
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static const struct mt76_reg_pair vals[] = {
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/* Copied from MediaTek reference source */
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{ MT_PBF_SYS_CTRL, 0x00080c00 },
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{ MT_PBF_CFG, 0x1efebcff },
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{ MT_FCE_PSE_CTRL, 0x00000001 },
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{ MT_MAC_SYS_CTRL, 0x00000000 },
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{ MT_MAX_LEN_CFG, 0x003e3f00 },
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{ MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
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{ MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
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{ MT_XIFS_TIME_CFG, 0x33a40d0a },
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{ MT_BKOFF_SLOT_CFG, 0x00000209 },
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{ MT_TBTT_SYNC_CFG, 0x00422010 },
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{ MT_PWR_PIN_CFG, 0x00000000 },
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{ 0x1238, 0x001700c8 },
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{ MT_TX_SW_CFG0, 0x00101001 },
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{ MT_TX_SW_CFG1, 0x00010000 },
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{ MT_TX_SW_CFG2, 0x00000000 },
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{ MT_TXOP_CTRL_CFG, 0x0400583f },
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{ MT_TX_RTS_CFG, 0x00ffff20 },
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{ MT_TX_TIMEOUT_CFG, 0x000a2290 },
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{ MT_TX_RETRY_CFG, 0x47f01f0f },
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{ MT_EXP_ACK_TIME, 0x002c00dc },
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{ MT_TX_PROT_CFG6, 0xe3f42004 },
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{ MT_TX_PROT_CFG7, 0xe3f42084 },
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{ MT_TX_PROT_CFG8, 0xe3f42104 },
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{ MT_PIFS_TX_CFG, 0x00060fff },
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{ MT_RX_FILTR_CFG, 0x00015f97 },
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{ MT_LEGACY_BASIC_RATE, 0x0000017f },
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{ MT_HT_BASIC_RATE, 0x00004003 },
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{ MT_PN_PAD_MODE, 0x00000003 },
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{ MT_TXOP_HLDR_ET, 0x00000002 },
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{ 0xa44, 0x00000000 },
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{ MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
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{ MT_TSO_CTRL, 0x00000000 },
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{ MT_AUX_CLK_CFG, 0x00000000 },
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{ MT_DACCLK_EN_DLY_CFG, 0x00000000 },
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{ MT_TX_ALC_CFG_4, 0x00000000 },
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{ MT_TX_ALC_VGA3, 0x00000000 },
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{ MT_TX_PWR_CFG_0, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_1, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_2, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_3, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_4, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_7, 0x3a3a3a3a },
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{ MT_TX_PWR_CFG_8, 0x0000003a },
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{ MT_TX_PWR_CFG_9, 0x0000003a },
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{ MT_EFUSE_CTRL, 0x0000d000 },
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{ MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
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{ MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
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{ MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
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{ MT_TX_SW_CFG3, 0x00000004 },
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{ MT_HT_FBK_TO_LEGACY, 0x00001818 },
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{ MT_VHT_HT_FBK_CFG1, 0xedcba980 },
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{ MT_PROT_AUTO_TX_CFG, 0x00830083 },
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{ MT_HT_CTRL_CFG, 0x000001ff },
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{ MT_TX_LINK_CFG, 0x00001020 },
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};
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struct mt76_reg_pair prot_vals[] = {
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{ MT_CCK_PROT_CFG, DEFAULT_PROT_CFG_CCK },
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{ MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG_OFDM },
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{ MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
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{ MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
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{ MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
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{ MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
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};
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mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));
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mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));
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}
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EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
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void mt76x2_init_txpower(struct mt76x02_dev *dev,
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struct ieee80211_supported_band *sband)
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{
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struct ieee80211_channel *chan;
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struct mt76x2_tx_power_info txp;
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struct mt76x02_rate_power t = {};
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int i;
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for (i = 0; i < sband->n_channels; i++) {
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chan = &sband->channels[i];
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mt76x2_get_power_info(dev, &txp, chan);
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mt76x2_get_rate_power(dev, &t, chan);
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chan->orig_mpwr = mt76x02_get_max_rate_power(&t) +
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txp.target_power;
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chan->orig_mpwr = DIV_ROUND_UP(chan->orig_mpwr, 2);
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/* convert to combined output power on 2x2 devices */
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chan->orig_mpwr += 3;
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chan->max_power = min_t(int, chan->max_reg_power,
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chan->orig_mpwr);
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}
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}
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EXPORT_SYMBOL_GPL(mt76x2_init_txpower);
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