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ca765beda7
Firmware sends CFR meta data through the WMI event WMI_PEER_CFR_CAPTURE_EVENT. Parse the meta data coming from the firmware and invoke correlate_and_relay function to correlate the CFR meta data with the CFR payload coming from the other WMI event WMI_PDEV_DMA_RING_BUF_RELEASE_EVENT. Release the buffer to user space once correlate and relay return success. Tested-on: IPQ8074 hw2.0 PCI IPQ8074 WLAN.HK.2.5.0.1-00991-QCAHKSWPL_SILICONZ-1 Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-04685-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1 Signed-off-by: Venkateswara Naralasetty <quic_vnaralas@quicinc.com> Co-developed-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com> Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com> Signed-off-by: Qian Zhang <qian.zhang@oss.qualcomm.com> Link: https://patch.msgid.link/20251230082520.3401007-7-qian.zhang@oss.qualcomm.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
309 lines
7.3 KiB
C
309 lines
7.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef ATH11K_CFR_H
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#define ATH11K_CFR_H
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#include "dbring.h"
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#include "wmi.h"
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#define ATH11K_CFR_NUM_RESP_PER_EVENT 1
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#define ATH11K_CFR_EVENT_TIMEOUT_MS 1
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#define ATH11K_CFR_NUM_RING_ENTRIES 1
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#define ATH11K_MAX_CFR_ENABLED_CLIENTS 10
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#define CFR_MAX_LUT_ENTRIES 136
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#define HOST_MAX_CHAINS 8
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enum ath11k_cfr_correlate_event_type {
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ATH11K_CORRELATE_DBR_EVENT,
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ATH11K_CORRELATE_TX_EVENT,
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};
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struct ath11k_sta;
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struct ath11k_per_peer_cfr_capture;
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#define ATH11K_CFR_START_MAGIC 0xDEADBEAF
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#define ATH11K_CFR_END_MAGIC 0xBEAFDEAD
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#define VENDOR_QCA 0x8cfdf0
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#define PLATFORM_TYPE_ARM 2
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enum ath11k_cfr_meta_version {
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ATH11K_CFR_META_VERSION_NONE,
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ATH11K_CFR_META_VERSION_1,
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ATH11K_CFR_META_VERSION_2,
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ATH11K_CFR_META_VERSION_3,
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ATH11K_CFR_META_VERSION_4,
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ATH11K_CFR_META_VERSION_MAX = 0xFF,
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};
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enum ath11k_cfr_data_version {
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ATH11K_CFR_DATA_VERSION_NONE,
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ATH11K_CFR_DATA_VERSION_1,
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ATH11K_CFR_DATA_VERSION_MAX = 0xFF,
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};
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enum ath11k_cfr_capture_ack_mode {
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ATH11K_CFR_CAPTURE_LEGACY_ACK,
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ATH11K_CFR_CAPTURE_DUP_LEGACY_ACK,
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ATH11K_CFR_CAPTURE_HT_ACK,
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ATH11K_CFR_CAPTURE_VHT_ACK,
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/*Always keep this at last*/
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ATH11K_CFR_CAPTURE_INVALID_ACK
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};
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enum ath11k_cfr_correlate_status {
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ATH11K_CORRELATE_STATUS_RELEASE,
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ATH11K_CORRELATE_STATUS_HOLD,
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ATH11K_CORRELATE_STATUS_ERR,
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};
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enum ath11k_cfr_preamble_type {
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ATH11K_CFR_PREAMBLE_TYPE_LEGACY,
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ATH11K_CFR_PREAMBLE_TYPE_HT,
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ATH11K_CFR_PREAMBLE_TYPE_VHT,
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};
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struct ath11k_cfr_peer_tx_param {
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u32 capture_method;
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u32 vdev_id;
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u8 peer_mac_addr[ETH_ALEN];
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u32 primary_20mhz_chan;
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u32 bandwidth;
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u32 phy_mode;
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u32 band_center_freq1;
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u32 band_center_freq2;
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u32 spatial_streams;
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u32 correlation_info_1;
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u32 correlation_info_2;
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u32 status;
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u32 timestamp_us;
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u32 counter;
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u32 chain_rssi[WMI_MAX_CHAINS];
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u16 chain_phase[WMI_MAX_CHAINS];
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u32 cfo_measurement;
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u8 agc_gain[HOST_MAX_CHAINS];
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u32 rx_start_ts;
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};
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struct cfr_metadata {
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u8 peer_addr[ETH_ALEN];
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u8 status;
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u8 capture_bw;
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u8 channel_bw;
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u8 phy_mode;
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u16 prim20_chan;
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u16 center_freq1;
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u16 center_freq2;
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u8 capture_mode;
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u8 capture_type;
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u8 sts_count;
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u8 num_rx_chain;
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u32 timestamp;
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u32 length;
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u32 chain_rssi[HOST_MAX_CHAINS];
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u16 chain_phase[HOST_MAX_CHAINS];
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u32 cfo_measurement;
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u8 agc_gain[HOST_MAX_CHAINS];
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u32 rx_start_ts;
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} __packed;
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struct ath11k_csi_cfr_header {
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u32 start_magic_num;
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u32 vendorid;
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u8 cfr_metadata_version;
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u8 cfr_data_version;
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u8 chip_type;
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u8 platform_type;
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u32 cfr_metadata_len;
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struct cfr_metadata meta_data;
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} __packed;
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#define TONES_IN_20MHZ 256
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#define TONES_IN_40MHZ 512
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#define TONES_IN_80MHZ 1024
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#define TONES_IN_160MHZ 2048 /* 160 MHz isn't supported yet */
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#define TONES_INVALID 0
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#define CFIR_DMA_HDR_INFO0_TAG GENMASK(7, 0)
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#define CFIR_DMA_HDR_INFO0_LEN GENMASK(13, 8)
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#define CFIR_DMA_HDR_INFO1_UPLOAD_DONE GENMASK(0, 0)
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#define CFIR_DMA_HDR_INFO1_CAPTURE_TYPE GENMASK(3, 1)
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#define CFIR_DMA_HDR_INFO1_PREAMBLE_TYPE GENMASK(5, 4)
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#define CFIR_DMA_HDR_INFO1_NSS GENMASK(8, 6)
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#define CFIR_DMA_HDR_INFO1_NUM_CHAINS GENMASK(11, 9)
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#define CFIR_DMA_HDR_INFO1_UPLOAD_PKT_BW GENMASK(14, 12)
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#define CFIR_DMA_HDR_INFO1_SW_PEER_ID_VALID GENMASK(15, 15)
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struct ath11k_cfr_dma_hdr {
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u16 info0;
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u16 info1;
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u16 sw_peer_id;
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u16 phy_ppdu_id;
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};
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struct ath11k_look_up_table {
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bool dbr_recv;
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bool tx_recv;
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u8 *data;
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u32 data_len;
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u16 dbr_ppdu_id;
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u16 tx_ppdu_id;
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dma_addr_t dbr_address;
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struct ath11k_csi_cfr_header header;
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struct ath11k_cfr_dma_hdr hdr;
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u64 txrx_tstamp;
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u64 dbr_tstamp;
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u32 header_length;
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u32 payload_length;
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struct ath11k_dbring_element *buff;
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};
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struct cfr_unassoc_pool_entry {
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u8 peer_mac[ETH_ALEN];
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u32 period;
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bool is_valid;
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};
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struct ath11k_cfr {
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struct ath11k_dbring rx_ring;
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/* Protects cfr data */
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spinlock_t lock;
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/* Protect for lut entries */
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spinlock_t lut_lock;
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struct ath11k_look_up_table *lut;
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struct dentry *enable_cfr;
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struct dentry *cfr_unassoc;
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struct rchan *rfs_cfr_capture;
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u8 cfr_enabled_peer_cnt;
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u32 lut_num;
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u64 tx_evt_cnt;
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u64 dbr_evt_cnt;
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u64 release_cnt;
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u64 tx_peer_status_cfr_fail;
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u64 tx_evt_status_cfr_fail;
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u64 tx_dbr_lookup_fail;
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u64 last_success_tstamp;
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u64 flush_dbr_cnt;
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u64 clear_txrx_event;
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u64 cfr_dma_aborts;
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bool enabled;
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enum wmi_phy_mode phymode;
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struct cfr_unassoc_pool_entry unassoc_pool[ATH11K_MAX_CFR_ENABLED_CLIENTS];
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};
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enum ath11k_cfr_capture_method {
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ATH11K_CFR_CAPTURE_METHOD_NULL_FRAME,
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ATH11K_CFR_CAPTURE_METHOD_NULL_FRAME_WITH_PHASE,
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ATH11K_CFR_CAPTURE_METHOD_PROBE_RESP,
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ATH11K_CFR_CAPTURE_METHOD_MAX,
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};
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enum ath11k_cfr_capture_bw {
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ATH11K_CFR_CAPTURE_BW_20,
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ATH11K_CFR_CAPTURE_BW_40,
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ATH11K_CFR_CAPTURE_BW_80,
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ATH11K_CFR_CAPTURE_BW_MAX,
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};
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#ifdef CONFIG_ATH11K_CFR
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int ath11k_cfr_init(struct ath11k_base *ab);
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void ath11k_cfr_deinit(struct ath11k_base *ab);
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void ath11k_cfr_lut_update_paddr(struct ath11k *ar, dma_addr_t paddr,
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u32 buf_id);
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void ath11k_cfr_decrement_peer_count(struct ath11k *ar,
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struct ath11k_sta *arsta);
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void ath11k_cfr_update_unassoc_pool_entry(struct ath11k *ar,
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const u8 *peer_mac);
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bool ath11k_cfr_peer_is_in_cfr_unassoc_pool(struct ath11k *ar,
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const u8 *peer_mac);
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void ath11k_cfr_update_unassoc_pool(struct ath11k *ar,
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struct ath11k_per_peer_cfr_capture *params,
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u8 *peer_mac);
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int ath11k_cfr_send_peer_cfr_capture_cmd(struct ath11k *ar,
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struct ath11k_sta *arsta,
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struct ath11k_per_peer_cfr_capture *params,
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const u8 *peer_mac);
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struct ath11k_dbring *ath11k_cfr_get_dbring(struct ath11k *ar);
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void ath11k_cfr_release_lut_entry(struct ath11k_look_up_table *lut);
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int ath11k_process_cfr_capture_event(struct ath11k_base *ab,
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struct ath11k_cfr_peer_tx_param *params);
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void ath11k_cfr_update_phymode(struct ath11k *ar, enum wmi_phy_mode phymode);
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#else
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static inline void ath11k_cfr_update_phymode(struct ath11k *ar,
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enum wmi_phy_mode phymode)
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{
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}
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static inline int ath11k_cfr_init(struct ath11k_base *ab)
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{
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return 0;
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}
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static inline void ath11k_cfr_deinit(struct ath11k_base *ab)
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{
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}
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static inline void ath11k_cfr_lut_update_paddr(struct ath11k *ar,
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dma_addr_t paddr, u32 buf_id)
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{
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}
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static inline void ath11k_cfr_decrement_peer_count(struct ath11k *ar,
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struct ath11k_sta *arsta)
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{
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}
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static inline void ath11k_cfr_update_unassoc_pool_entry(struct ath11k *ar,
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const u8 *peer_mac)
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{
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}
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static inline bool
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ath11k_cfr_peer_is_in_cfr_unassoc_pool(struct ath11k *ar, const u8 *peer_mac)
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{
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return false;
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}
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static inline void
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ath11k_cfr_update_unassoc_pool(struct ath11k *ar,
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struct ath11k_per_peer_cfr_capture *params,
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u8 *peer_mac)
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{
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}
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static inline int
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ath11k_cfr_send_peer_cfr_capture_cmd(struct ath11k *ar,
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struct ath11k_sta *arsta,
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struct ath11k_per_peer_cfr_capture *params,
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const u8 *peer_mac)
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{
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return 0;
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}
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static inline void ath11k_cfr_release_lut_entry(struct ath11k_look_up_table *lut)
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{
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}
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static inline
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struct ath11k_dbring *ath11k_cfr_get_dbring(struct ath11k *ar)
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{
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return NULL;
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}
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static inline
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int ath11k_process_cfr_capture_event(struct ath11k_base *ab,
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struct ath11k_cfr_peer_tx_param *params)
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{
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return 0;
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}
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#endif /* CONFIG_ATH11K_CFR */
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#endif /* ATH11K_CFR_H */
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