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d0ce9fd7ea
In order for us to support a PCS device we need to add an MDIO bus to allow the drivers to have access to the registers for the device. This change adds such an interface. The interface will consist of 2 PHY addrs, the first one consisting of a PMD and PCS, and the second just being a PCS. There is a need for 2 PHYs addrs due to the fact that in order to support the 50GBase-CR2 mode we will need to access and configure the PCS vendor registers and RSFEC registers from the second lane identical to the first. Signed-off-by: Alexander Duyck <alexanderduyck@fb.com> Link: https://patch.msgid.link/176374324532.959489.15389723111560978054.stgit@ahduyck-xeon-server.home.arpa Signed-off-by: Paolo Abeni <pabeni@redhat.com>
29 lines
555 B
Makefile
29 lines
555 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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# Copyright (c) Meta Platforms, Inc. and affiliates.
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#
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# Makefile for the Meta(R) Host Network Interface
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#
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obj-$(CONFIG_FBNIC) += fbnic.o
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fbnic-y := fbnic_csr.o \
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fbnic_debugfs.o \
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fbnic_devlink.o \
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fbnic_ethtool.o \
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fbnic_fw.o \
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fbnic_fw_log.o \
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fbnic_hw_stats.o \
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fbnic_hwmon.o \
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fbnic_irq.o \
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fbnic_mac.o \
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fbnic_netdev.o \
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fbnic_pci.o \
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fbnic_phylink.o \
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fbnic_rpc.o \
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fbnic_mdio.o \
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fbnic_time.o \
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fbnic_tlv.o \
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fbnic_txrx.o \
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# End of objects
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