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31ddf7965a
At the end of the probe, trigger hard reset, initialize and schedule the after-reset task. If the reset is complete in a pre-determined time, initialize the default mailbox, through which other resources will be negotiated. Co-developed-by: Amritha Nambiar <amritha.nambiar@intel.com> Signed-off-by: Amritha Nambiar <amritha.nambiar@intel.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Tested-by: Bharath R <Bharath.r@intel.com> Signed-off-by: Larysa Zaremba <larysa.zaremba@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2025 Intel Corporation */
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#include "ixd.h"
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#include "ixd_lan_regs.h"
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/**
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* ixd_ctlq_reg_init - Initialize default mailbox registers
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* @adapter: PCI device driver-specific private data
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* @ctlq_reg_tx: Transmit queue registers info to be filled
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* @ctlq_reg_rx: Receive queue registers info to be filled
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*/
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void ixd_ctlq_reg_init(struct ixd_adapter *adapter,
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struct libie_ctlq_reg *ctlq_reg_tx,
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struct libie_ctlq_reg *ctlq_reg_rx)
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{
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struct libie_mmio_info *mmio_info = &adapter->cp_ctx.mmio_info;
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*ctlq_reg_tx = (struct libie_ctlq_reg) {
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.head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQH),
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.tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQT),
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.len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQLEN),
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.addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAH),
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.addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAL),
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.len_mask = PF_FW_ATQLEN_ATQLEN_M,
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.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M,
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.head_mask = PF_FW_ATQH_ATQH_M,
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};
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*ctlq_reg_rx = (struct libie_ctlq_reg) {
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.head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQH),
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.tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQT),
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.len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQLEN),
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.addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAH),
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.addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAL),
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.len_mask = PF_FW_ARQLEN_ARQLEN_M,
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.len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M,
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.head_mask = PF_FW_ARQH_ARQH_M,
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};
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}
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static const struct ixd_reset_reg ixd_reset_reg = {
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.rstat = PFGEN_RSTAT,
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.rstat_m = PFGEN_RSTAT_PFR_STATE_M,
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.rstat_ok_v = 0b01,
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.rtrigger = PFGEN_CTRL,
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.rtrigger_m = PFGEN_CTRL_PFSWR,
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};
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/**
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* ixd_trigger_reset - Trigger PFR reset
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* @adapter: the device with mapped reset register
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*/
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void ixd_trigger_reset(struct ixd_adapter *adapter)
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{
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void __iomem *addr;
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u32 reg_val;
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addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
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ixd_reset_reg.rtrigger);
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reg_val = readl(addr);
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writel(reg_val | ixd_reset_reg.rtrigger_m, addr);
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}
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/**
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* ixd_check_reset_complete - Check if the PFR reset is completed
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* @adapter: CPF being reset
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*
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* Return: %true if the register read indicates reset has been finished,
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* %false otherwise
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*/
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bool ixd_check_reset_complete(struct ixd_adapter *adapter)
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{
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u32 reg_val, reset_status;
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void __iomem *addr;
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addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
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ixd_reset_reg.rstat);
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reg_val = readl(addr);
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reset_status = reg_val & ixd_reset_reg.rstat_m;
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/* 0xFFFFFFFF might be read if the other side hasn't cleared
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* the register for us yet.
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*/
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if (reg_val != GENMASK(31, 0) &&
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reset_status == ixd_reset_reg.rstat_ok_v)
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return true;
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return false;
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}
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