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Add full CPI (Converged PHY Interface) command handling required for E825C devices. The CPI interface allows the driver to interact with PHY-side control logic through the LM/PHY command registers, including enabling/disabling/selection of PHY reference clock. This patch introduces: - a new CPI subsystem (ice_cpi.c / ice_cpi.h) implementing the CPI request/acknowledge state machine, including REQ/ACK protocol, command execution, and response handling - helper functions for reading/writing PHY registers over Sideband Queue - CPI command execution API (ice_cpi_exec) and a helper for enabling or disabling Tx reference clocks (CPI 0xF1 opcode 'Config PHY clocking') - assurance of CPI transaction serialization into the CPI core. CPI REQ/ACK is a multi-step handshake and must be executed atomically per PHY. Centralize the lock in ice_cpi_exec() and use adapter-scoped per-PHY mutexes, which match the hardware sharing model across PFs. - addition of the non-posted write opcode (wr_np) to SBQ - Makefile integration to build CPI support together with the PTP stack This provides the infrastructure necessary to support PHY-side configuration flows on E825C and is required for advanced link control and Tx reference clock management. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-12-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2026 Intel Corporation */
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#ifndef _ICE_CPI_H_
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#define _ICE_CPI_H_
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#include "ice_type.h"
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#include "ice_ptp_hw.h"
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#define CPI0_PHY1_CMD_DATA 0x7FD028
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#define CPI0_LM1_CMD_DATA 0x7FD024
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#define CPI_RETRIES_COUNT 10
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#define CPI_RETRIES_CADENCE_MS 100
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/* CPI PHY CMD DATA register (CPI0_PHY1_CMD_DATA) */
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#define CPI_PHY_CMD_DATA_M GENMASK(15, 0)
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#define CPI_PHY_CMD_OPCODE_M GENMASK(23, 16)
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#define CPI_PHY_CMD_PORTLANE_M GENMASK(26, 24)
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#define CPI_PHY_CMD_RSVD_M GENMASK(29, 27)
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#define CPI_PHY_CMD_ERROR_M BIT(30)
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#define CPI_PHY_CMD_ACK_M BIT(31)
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/* CPI LM CMD DATA register (CPI0_LM1_CMD_DATA) */
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#define CPI_LM_CMD_DATA_M GENMASK(15, 0)
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#define CPI_LM_CMD_OPCODE_M GENMASK(23, 16)
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#define CPI_LM_CMD_PORTLANE_M GENMASK(26, 24)
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#define CPI_LM_CMD_RSVD_M GENMASK(28, 27)
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#define CPI_LM_CMD_GET_SET_M BIT(29)
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#define CPI_LM_CMD_REQ_M BIT(31)
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#define CPI_OPCODE_PHY_CLK 0xF1
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#define CPI_OPCODE_PHY_CLK_PHY_SEL_M GENMASK(9, 6)
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#define CPI_OPCODE_PHY_CLK_REF_CTRL_M GENMASK(5, 4)
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#define CPI_OPCODE_PHY_CLK_DISABLE 1
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#define CPI_OPCODE_PHY_CLK_ENABLE 2
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#define CPI_OPCODE_PHY_CLK_REF_SEL_M GENMASK(3, 0)
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#define CPI_LM_CMD_REQ 1
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struct ice_cpi_cmd {
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u8 port;
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u8 opcode;
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u16 data;
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bool set;
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};
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struct ice_cpi_resp {
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u8 port;
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u8 opcode;
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u16 data;
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};
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int ice_cpi_exec(struct ice_hw *hw, u8 phy,
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const struct ice_cpi_cmd *cmd,
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struct ice_cpi_resp *resp);
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int ice_cpi_ena_dis_clk_ref(struct ice_hw *hw, u8 phy,
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enum ice_e825c_ref_clk clk, bool enable);
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#endif /* _ICE_CPI_H_ */
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