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The buffer pool is a quantity of memory available for buffering a group of flows (e.g. frames having the same priority, frames received from the same port), while waiting to be transmitted on a port. The buffer pool tracks internal memory consumption with upper bound limits and optionally a non-shared portion when associated with a shared buffer pool. Currently the shared buffer pool is not supported, it will be added in the future. For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is allocated two buffer pools. For frames with priorities of 0 to 3, they will be mapped to the first buffer pool; For frames with priorities of 4 to 7, they will be mapped to the second buffer pool. Each buffer pool has a flow control on threshold and a flow control off threshold. By setting these threshold, add the flow control support to each port. Signed-off-by: Wei Fang <wei.fang@nxp.com> Link: https://patch.msgid.link/20260518082506.1318236-14-wei.fang@nxp.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
88 lines
2.0 KiB
C
88 lines
2.0 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* NXP NETC switch driver
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* Copyright 2025-2026 NXP
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*/
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#include "netc_switch.h"
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struct netc_switch_platform {
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u16 revision;
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const struct netc_switch_info *info;
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};
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static void imx94_switch_phylink_get_caps(int port,
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struct phylink_config *config)
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{
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config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_1000FD;
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switch (port) {
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case 0 ... 1:
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__set_bit(PHY_INTERFACE_MODE_SGMII,
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config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_2500BASEX,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_2500FD;
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fallthrough;
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case 2:
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config->mac_capabilities |= MAC_10 | MAC_100;
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__set_bit(PHY_INTERFACE_MODE_MII,
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config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_RMII,
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config->supported_interfaces);
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/* Port 0 and 1 do not support REVMII */
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if (port == 2)
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__set_bit(PHY_INTERFACE_MODE_REVMII,
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config->supported_interfaces);
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phy_interface_set_rgmii(config->supported_interfaces);
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break;
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case 3: /* CPU port */
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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config->supported_interfaces);
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config->mac_capabilities |= MAC_10FD | MAC_100FD |
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MAC_2500FD;
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break;
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default:
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break;
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}
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}
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static const struct netc_switch_info imx94_info = {
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.num_ports = 4,
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.phylink_get_caps = imx94_switch_phylink_get_caps,
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};
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static const struct netc_switch_platform netc_platforms[] = {
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{ .revision = NETC_SWITCH_REV_4_3, .info = &imx94_info, },
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{ }
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};
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static const struct netc_switch_info *
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netc_switch_get_info(struct netc_switch *priv)
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{
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int i;
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/* Matching based on IP revision */
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for (i = 0; i < ARRAY_SIZE(netc_platforms); i++) {
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if (priv->revision == netc_platforms[i].revision)
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return netc_platforms[i].info;
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}
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return NULL;
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}
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int netc_switch_platform_probe(struct netc_switch *priv)
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{
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const struct netc_switch_info *info = netc_switch_get_info(priv);
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if (!info) {
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dev_err(priv->dev, "Cannot find switch platform info\n");
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return -EINVAL;
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}
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priv->info = info;
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return 0;
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}
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