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8bf5e84998
Add support for the ISSEI (Intel Silicon Security Engine Interface) HECI PCI devices. Add the necessary PCI handling routines, hardware definitions, register mappings and hardware access routines. This enables the communication via HECI PCI device advertized by BIOS. Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Co-developed-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://patch.msgid.link/20260513-issei-for-upstream-v1-4-f590038678f9@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2023-2026 Intel Corporation */
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#ifndef _ISSEI_HW_HECI_H_
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#define _ISSEI_HW_HECI_H_
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "issei_dev.h"
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/*
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* hw_heci_cfg - issei heci device configuration
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*
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* @dma_length: DMA area length
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*/
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struct hw_heci_cfg {
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const struct issei_dma_length dma_length;
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};
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/**
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* struct issei_heci_hw - issei heci hw specific data
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*
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* @cfg: per device generation config and ops
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* @mem_addr: io memory address
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* @irq: device irq number
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* @access_lock: spinlock to protect hw access
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* @hbuf_depth: depth of hardware host/write buffer in slots
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*/
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struct issei_heci_hw {
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const struct hw_heci_cfg *cfg;
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void __iomem *mem_addr;
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int irq;
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spinlock_t access_lock;
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u8 hbuf_depth;
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};
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#define to_heci_hw(dev) ((struct issei_heci_hw *)(dev)->hw)
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const struct hw_heci_cfg *issei_heci_get_cfg(kernel_ulong_t idx);
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const struct issei_hw_ops *issei_heci_get_ops(void);
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void issei_heci_dev_init(struct issei_device *idev,
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void __iomem *mem_addr, const struct hw_heci_cfg *cfg);
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irqreturn_t issei_heci_irq_quick_handler(int irq, void *dev_id);
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#endif /* _ISSEI_HW_HECI_H_ */
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